Issued Patents 2017
Showing 1–25 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9851971 | Latent modification instruction for transactional execution | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2017-12-26 |
| 9852014 | Deferral instruction for managing transactional aborts in transactional memory computing environments | Chung-Lung K. Shum | 2017-12-26 |
| 9851969 | Function virtualization facility for function query of a processor | Dan F. Greiner, Damian L. Osisek | 2017-12-26 |
| 9851978 | Restricted instructions in transactional execution | Dan F. Greiner, Christian Jacobi | 2017-12-26 |
| 9846593 | Predicting the length of a transaction | Jonathan D. Bradbury, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more | 2017-12-19 |
| 9823924 | Vector element rotate and insert under mask instruction | Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz | 2017-11-21 |
| 9823926 | Vector element rotate and insert under mask instruction | Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz | 2017-11-21 |
| 9817693 | Coherence protocol augmentation to indicate transaction status | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Christian Jacobi, Valentina Salapura +1 more | 2017-11-14 |
| 9811337 | Transaction abort processing | Dan F. Greiner, Christian Jacobi | 2017-11-07 |
| 9804847 | Thread context preservation in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2017-10-31 |
| 9804849 | Space reduction in processor stressmark generation | Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu | 2017-10-31 |
| 9804846 | Thread context preservation in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2017-10-31 |
| 9804970 | Invalidating a range of two or more translation table entries and instruction therefor | Lisa C. Heller, Erwin Pfeffer, Kenneth E. Plambeck | 2017-10-31 |
| 9798546 | Space reduction in processor stressmark generation | Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu | 2017-10-24 |
| 9792125 | Saving/restoring selected registers in transactional processing | Dan F. Greiner, Christian Jacobi | 2017-10-17 |
| 9792124 | Speculative branch handling for transaction abort | Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito | 2017-10-17 |
| 9778932 | Vector generate mask instruction | Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz | 2017-10-03 |
| 9772854 | Selectively controlling instruction execution in transactional processing | Dan F. Greiner, Christian Jacobi, Robert R. Rogers | 2017-09-26 |
| 9772843 | Vector find element equal instruction | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz | 2017-09-26 |
| 9772867 | Control area for managing multiple threads in a computer | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2017-09-26 |
| 9772786 | Address probing for transaction | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael +2 more | 2017-09-26 |
| 9772874 | Prioritization of transactions based on execution by transactional core with super core indicator | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2017-09-26 |
| 9766829 | Address probing for transaction | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael +2 more | 2017-09-19 |
| 9766925 | Transactional processing | Dan F. Greiner, Christian Jacobi | 2017-09-19 |
| 9760511 | Efficient interruption routing for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +7 more | 2017-09-12 |