| 9846593 |
Predicting the length of a transaction |
Jonathan D. Bradbury, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum +1 more |
2017-12-19 |
| 9830185 |
Indicating nearing the completion of a transaction |
Jonathan D. Bradbury, Dan F. Greiner, Michael K. Gschwind, Chung-Lung K. Shum |
2017-11-28 |
| 9824040 |
Signal interrupts in a transactional memory system |
Paul E. McKenney, Michael Wong |
2017-11-21 |
| 9824039 |
Signal interrupts in a transactional memory system |
Paul E. McKenney, Michael Wong |
2017-11-21 |
| 9772786 |
Address probing for transaction |
Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Eric M. Schwarz +2 more |
2017-09-26 |
| 9766829 |
Address probing for transaction |
Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Eric M. Schwarz +2 more |
2017-09-19 |
| 9766950 |
Methods for single-owner multi-consumer work queues for repeatable tasks |
Vijay A. Saraswat, Martin Vechev |
2017-09-19 |
| 9760397 |
Interprocessor memory status communication |
Dan F. Greiner, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel |
2017-09-12 |
| 9753764 |
Alerting hardware transactions that are about to run out of space |
Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura |
2017-09-05 |
| 9740616 |
Multi-granular cache management in multi-processor computing environments |
Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more |
2017-08-22 |
| 9720713 |
Using hardware transactional memory for implementation of queue operations |
Jing Zheng |
2017-08-01 |
| 9720725 |
Prefetching of discontiguous storage locations as part of transactional execution |
Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more |
2017-08-01 |
| 9696928 |
Memory transaction having implicit ordering effects |
Harold W. Cain, III, Kattamuri Ekanadham, Pratap C. Pattnaik, Derek E. Williams |
2017-07-04 |
| 9696927 |
Memory transaction having implicit ordering effects |
Harold W. Cain, III, Kattamuri Ekanadham, Pratap C. Pattnaik, Derek E. Williams |
2017-07-04 |
| 9690556 |
Code optimization to enable and disable coalescing of memory transactions |
Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum |
2017-06-27 |
| 9645879 |
Salvaging hardware transactions with instructions |
Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz |
2017-05-09 |
| 9639415 |
Salvaging hardware transactions with instructions |
Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz |
2017-05-02 |
| 9632820 |
Prefetching of discontiguous storage locations in anticipation of transactional execution |
Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more |
2017-04-25 |
| 9626187 |
Transactional memory system supporting unbroken suspended execution |
Harold W. Cain, III, Bradly G. Frey, Benjamin Herrenschmidt, Hung Q. Le, Cathy May +4 more |
2017-04-18 |
| 9619383 |
Dynamic predictor for coalescing memory transactions |
Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Eric M. Schwarz |
2017-04-11 |
| 9563468 |
Interprocessor memory status communication |
Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel |
2017-02-07 |
| 9563467 |
Interprocessor memory status communication |
Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel |
2017-02-07 |
| 9547595 |
Salvaging lock elision transactions |
Harold W. Cain, III, Michael K. Gschwind, Chung-Lung K. Shum |
2017-01-17 |
| 9535696 |
Instruction to cancel outstanding cache prefetches |
Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum |
2017-01-03 |
