| 9851979 |
Split-level history buffer in a computer processing unit |
Dung Q. Nguyen, David R. Terry |
2017-12-26 |
| 9798577 |
Transactional storage accesses supporting differing priority levels |
Guy L. Guthrie, William J. Starke, Derek E. Williams |
2017-10-24 |
| 9792147 |
Transactional storage accesses supporting differing priority levels |
Guy L. Guthrie, William J. Starke, Derek E. Williams |
2017-10-17 |
| 9720696 |
Independent mapping of threads |
Sam Gat-Shang Chu, Markus Kaltenbach, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen +1 more |
2017-08-01 |
| 9703561 |
Thread transition management |
Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James Allan Kahle, Dung Q. Nguyen |
2017-07-11 |
| 9690586 |
Processing of multiple instruction streams in a parallel slice processor |
Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2017-06-27 |
| 9690585 |
Parallel slice processor with dynamic instruction stream mapping |
Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2017-06-27 |
| 9672043 |
Processing of multiple instruction streams in a parallel slice processor |
Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2017-06-06 |
| 9665372 |
Parallel slice processor with dynamic instruction stream mapping |
Lee Evan Eisen, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more |
2017-05-30 |
| 9626256 |
Determining failure context in hardware transactional memories |
Harold W. Cain, III, Bradly G. Frey, Cathy May |
2017-04-18 |
| 9626187 |
Transactional memory system supporting unbroken suspended execution |
Harold W. Cain, III, Bradly G. Frey, Benjamin Herrenschmidt, Cathy May, Maged M. Michael +4 more |
2017-04-18 |
| 9619345 |
Apparatus for determining failure context in hardware transactional memories |
Harold W. Cain, III, Bradly G. Frey, Cathy May |
2017-04-11 |
