Issued Patents 2017
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9817693 | Coherence protocol augmentation to indicate transaction status | Harold W. Cain, III, Michael K. Gschwind, Christian Jacobi, Valentina Salapura, Eric M. Schwarz +1 more | 2017-11-14 |
| 9804847 | Thread context preservation in a multithreading computer system | Jonathan D. Bradbury, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2017-10-31 |
| 9804846 | Thread context preservation in a multithreading computer system | Jonathan D. Bradbury, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2017-10-31 |
| 9798545 | Anticipated prefetching for a parent core in a multi-core chip | Brian R. Prasky, Steven R. Carlough, Christopher A. Krygowski, Chung-Lung K. Shum | 2017-10-24 |
| 9792120 | Anticipated prefetching for a parent core in a multi-core chip | Brian R. Prasky, Steven R. Carlough, Christopher A. Krygowski, Chung-Lung K. Shum | 2017-10-17 |
| 9772867 | Control area for managing multiple threads in a computer | Jonathan D. Bradbury, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +4 more | 2017-09-26 |
| 9772944 | Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2017-09-26 |
| 9772874 | Prioritization of transactions based on execution by transactional core with super core indicator | Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2017-09-26 |
| 9772786 | Address probing for transaction | Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +2 more | 2017-09-26 |
| 9766896 | Optimizing grouping of instructions | Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Jr., Eric M. Schwarz +1 more | 2017-09-19 |
| 9766829 | Address probing for transaction | Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +2 more | 2017-09-19 |
| 9760511 | Efficient interruption routing for a multithreaded processor | Jonathan D. Bradbury, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller +7 more | 2017-09-12 |
| 9753764 | Alerting hardware transactions that are about to run out of space | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2017-09-05 |
| 9740616 | Multi-granular cache management in multi-processor computing environments | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2017-08-22 |
| 9720725 | Prefetching of discontiguous storage locations as part of transactional execution | Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2017-08-01 |
| 9710271 | Collecting transactional execution characteristics during transactional execution | Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2017-07-18 |
| 9710278 | Optimizing grouping of instructions | Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Jr., Eric M. Schwarz +1 more | 2017-07-18 |
| 9703560 | Collecting transactional execution characteristics during transactional execution | Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2017-07-11 |
| 9690623 | Regulating hardware speculative processing around a transaction | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2017-06-27 |
| 9690556 | Code optimization to enable and disable coalescing of memory transactions | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2017-06-27 |
| 9684537 | Regulating hardware speculative processing around a transaction | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2017-06-20 |
| 9665376 | Sharing program interrupt logic in a multithreaded processor | Khary J. Alexander, Michael Billeci, Mark S. Farrell, Christian Jacobi, Timothy J. Slegel | 2017-05-30 |
| 9645879 | Salvaging hardware transactions with instructions | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2017-05-09 |
| 9639415 | Salvaging hardware transactions with instructions | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2017-05-02 |
| 9632820 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2017-04-25 |