Issued Patents 2017
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9804849 | Space reduction in processor stressmark generation | Ramon Bertran, Pradip Bose, Timothy J. Slegel | 2017-10-31 |
| 9798546 | Space reduction in processor stressmark generation | Ramon Bertran, Pradip Bose, Timothy J. Slegel | 2017-10-24 |
| 9740497 | Processor with memory-embedded pipeline for table-driven computation | Pradip Bose, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan | 2017-08-22 |
| 9740496 | Processor with memory-embedded pipeline for table-driven computation | Pradip Bose, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan | 2017-08-22 |
| 9727434 | Generation and application of stressmarks in a computer system | Ramon Bertran, Pradip Bose, Timothy J. Slegel | 2017-08-08 |
| 9710044 | Power shifting in multicore platforms by varying SMT levels | Pradip Bose, Hubertus Franke, Priyanka Tembey, Dilma M. Da Silva | 2017-07-18 |
| 9696379 | Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers | Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas | 2017-07-04 |
| 9690555 | Optimization of application workflow in mobile embedded devices | Ramon Bertran Monfort, Pradip Bose, Chen-Yong Cher, Hans M. Jacobson, William Jinho Song +3 more | 2017-06-27 |
| 9652243 | Predicting out-of-order instruction level parallelism of threads in a multi-threaded processor | Ioana Monica Burcea, Brian R. Prasky, Vijayalakshmi Srinivasan | 2017-05-16 |
| 9645935 | Intelligent bandwidth shifting mechanism | Pradip Bose, Victor Javier Jimenez Perez, Francis Patrick O'Connell | 2017-05-09 |
| 9632560 | Delaying execution in a processor to increase power savings | Pradip Bose, Hans M. Jacobson, Augusto J. Vega | 2017-04-25 |
| 9632559 | Delaying execution in a processor to increase power savings | Pradip Bose, Hans M. Jacobson, Augusto J. Vega | 2017-04-25 |
| 9626293 | Single-thread cache miss rate estimation | James J. Bonanno, Brian W. Curran, Willm Hinrichs, Christian Jacobi, Brian R. Prasky +4 more | 2017-04-18 |
| 9619385 | Single thread cache miss rate estimation | James J. Bonanno, Brian W. Curran, Willm Hinrichs, Christian Jacobi, Brian R. Prasky +4 more | 2017-04-11 |
| 9618999 | Idle-aware margin adaption | Ramon Bertran, Pradip Bose, Timothy J. Slegel | 2017-04-11 |
| 9588863 | Generation and application of stressmarks in a computer system | Ramon Bertran, Pradip Bose, Timothy J. Slegel | 2017-03-07 |
| 9575867 | Processor stressmarks generation | Ramon Bertran, Pradip Bose | 2017-02-21 |
| 9575868 | Processor stressmarks generation | Ramon Bertran, Pradip Bose | 2017-02-21 |
| 9569402 | 3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components | Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas | 2017-02-14 |