Issued Patents 2016
Showing 1–25 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530785 | Three-dimensional memory devices having a single layer channel and methods of making thereof | Sateesh Koka, Zhenyu Lu, Wei Zhao, Ching-Huang Lu, Henry Chien +6 more | 2016-12-27 |
| 9530506 | NAND boosting using dynamic ramping of word line voltages | Peter Rabkin, Masaaki Higashitani | 2016-12-27 |
| 9490262 | Selective removal of charge-trapping layer for select gate transistor and dummy memory cells in 3D stacked memory | Liang Pang | 2016-11-08 |
| 9466382 | Compensation for sub-block erase | Chris Avila, Man Lung Mui | 2016-10-11 |
| 9466369 | Word line-dependent ramping of pass voltage and program voltage for three-dimensional memory | Liang Pang, Jiahui Yuan, Jingjian Ren | 2016-10-11 |
| 9460805 | Word line dependent channel pre-charge for memory | Liang Pang, Jiahui Yuan | 2016-10-04 |
| 9455263 | Three dimensional NAND device with channel contacting conductive source line and method of making thereof | Yanli Zhang, Go Shoji, Johann Alsmeier, Jayavel Pachamuthu, Jiahui Yuan | 2016-09-27 |
| 9443605 | Temperature dependent voltage to unselected drain side select transistor during program of 3D NAND | Jian Chen, Jiahui Yuan | 2016-09-13 |
| 9437305 | Programming memory with reduced short-term charge loss | Ching-Huang Lu, Liang Pang, Tien-Chien Kuo | 2016-09-06 |
| 9437318 | Adaptive program pulse duration based on temperature | Jiahui Yuan, Jian Chen | 2016-09-06 |
| 9412463 | Reducing hot electron injection type of read disturb in 3D non-volatile memory for edge word lines | Hong-Yan Chen | 2016-08-09 |
| 9406391 | Method of reducing hot electron injection type of read disturb in dummy memory cells | Hong-Yan Chen, Wei Zhao | 2016-08-02 |
| 9406693 | Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory | Liang Pang | 2016-08-02 |
| 9406690 | Contact for vertical memory with dopant diffusion stopper and associated fabrication method | Liang Pang, Jayavel Pachamuthu | 2016-08-02 |
| 9406387 | Charge redistribution during erase in charge trapping memory | Jiahui Yuan, Ching-Huang Lu | 2016-08-02 |
| RE46056 | Programming non-volatile storage with fast bit detection and verify skip | Changyuan Chen, Jeffrey W. Lutze, Hua-Ling Cynthia Hsu | 2016-07-05 |
| 9378832 | Method to recover cycling damage and improve long term data retention | Ching-Huang Lu, Zhengyi Zhang, Wei Zhao, Jian Chen | 2016-06-28 |
| 9368509 | Three-dimensional memory structure having self-aligned drain regions and methods of making thereof | Liang Pang, Jayavel Pachamuthu | 2016-06-14 |
| 9361993 | Method of reducing hot electron injection type of read disturb in memory | Hong-Yan Chen, Wei Zhao, Charles See Yeung Kwong | 2016-06-07 |
| 9355735 | Data recovery in a 3D memory device with a short circuit between word lines | Jian Chen, Jiahui Yuan, Charles See Yeung Kwong | 2016-05-31 |
| 9349478 | Read with look-back combined with programming with asymmetric boosting in memory | Jiahui Yuan, Charles See Yeung Kwong, Hong-Yan Chen, Liang Pang | 2016-05-24 |
| 9343141 | Reprogramming memory with single program pulse per data state | Liang Pang | 2016-05-17 |
| 9343156 | Balancing programming speeds of memory cells in a 3D stacked memory | Man Lung Mui, Yongke Sun | 2016-05-17 |
| 9343159 | Avoiding unintentional program or erase of a select gate transistor | Liang Pang | 2016-05-17 |
| 9343171 | Reduced erase-verify voltage for first-programmed word line in a memory device | Yongke Sun | 2016-05-17 |