Issued Patents 2016
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530876 | Strained semiconductor nanowire | Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight | 2016-12-27 |
| 9515247 | Sacrificial shorting straps for superconducting qubits | Douglas T. McClure, III | 2016-12-06 |
| 9496338 | Wire-last gate-all-around nanowire FET | Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2016-11-15 |
| 9496184 | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology | Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight | 2016-11-15 |
| 9484205 | Semiconductor device having self-aligned gate contacts | Paul Chang, Michael A. Guillorn | 2016-11-01 |
| 9472499 | Self-aligned pitch split for unidirectional metal wiring | Michael A. Guillorn, Eric A. Joseph, Hiroyuki Miyazoe | 2016-10-18 |
| 9466534 | Cointegration of directed self assembly and sidewall image transfer patterning for sublithographic patterning with improved design flexibility | Markus Brink, Michael A. Guillorn, Hsinuyu Tsai | 2016-10-11 |
| 9443949 | Techniques for multiple gate workfunctions for a nanowire CMOS technology | Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2016-09-13 |
| 9444029 | Piezoelectronic transistor with co-planar common and gate electrodes | Brian A. Bryce, Marcelo A. Kuroda | 2016-09-13 |
| 9443951 | Embedded planar source/drain stressors for a finFET including a plurality of fins | Paul Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2016-09-13 |
| 9437613 | Multiple VT in III-V FETs | Isaac Lauer, Amlan Majumdar, Jeffrey W. Sleight | 2016-09-06 |
| 9419201 | Integrating a piezoresistive element in a piezoelectronic transistor | Brian A. Bryce, Matthew W. Copel, Marcelo A. Kuroda | 2016-08-16 |
| 9419203 | Passivation and alignment of piezoelectronic transistor piezoresistor | Brian A. Bryce, Matthew W. Copel, Marcelo A. Kuroda | 2016-08-16 |
| 9391163 | Stacked planar double-gate lamellar field-effect transistor | Michael A. Guillorn, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight | 2016-07-12 |
| 9385027 | Sublithographic Kelvin structure patterned with DSA | Michael A. Guillorn, Chung-Hsun Lin, HsinYu Tsai | 2016-07-05 |
| 9385026 | Sublithographic Kelvin structure patterned with DSA | Michael A. Guillorn, Chung-Hsun Lin, HsinYu Tsai | 2016-07-05 |
| 9368599 | Graphene/nanostructure FET with self-aligned contact and gate | Isaac Lauer, Jeffrey W. Sleight | 2016-06-14 |
| 9368502 | Replacement gate multigate transistor for embedded DRAM | Leland Chang, Michael A. Guillorn, Wilfried E. Haensch | 2016-06-14 |
| 9362354 | Tuning gate lengths in semiconductor device structures | Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2016-06-07 |
| 9349640 | Electrode pair fabrication using directed self assembly of diblock copolymers | Michael A. Guillorn, Hiroyuki Miyazoe, Adam M. Pyzyna, HsinYu Tsai | 2016-05-24 |
| 9318692 | Self-limited crack etch to prevent device shorting | Brian A. Bryce, Hiroyuki Miyazoe | 2016-04-19 |
| 9306164 | Electrode pair fabrication using directed self assembly of diblock copolymers | Michael A. Guillorn, Hiroyuki Miyazoe, Adam M. Pyzyna, HsinYu Tsai | 2016-04-05 |
| 9299615 | Multiple VT in III-V FETs | Isaac Lauer, Amlan Majumdar, Jeffrey W. Sleight | 2016-03-29 |
| 9293687 | Passivation and alignment of piezoelectronic transistor piezoresistor | Brian A. Bryce, Matthew W. Copel, Marcelo A. Kuroda | 2016-03-22 |
| 9287489 | Piezoelectronic transistor with co-planar common and gate electrodes | Brian A. Bryce, Marcelo A. Kuroda | 2016-03-15 |