Issued Patents 2016
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9443929 | Shallow trench isolation structure having a nitride plug | Byeong Y. Kim | 2016-09-13 |
| 9437496 | Merged source drain epitaxy | Michael P. Chudzik, Brian J. Greene, Edward P. Maciejewski, Kevin McStay, Chengwen Pei +1 more | 2016-09-06 |
| 9425079 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Arvind Kumar, Renee T. Mo | 2016-08-23 |
| 9412667 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Claude Ortolland, Jonathan T. Shaw | 2016-08-09 |
| 9401325 | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication | Anthony I. Chou, Arvind Kumar, Renee T. Mo | 2016-07-26 |
| 9287399 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt +6 more | 2016-03-15 |
| 9269786 | Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors | Anthony I. Chou, Arvind Kumar, Claude Ortolland, Kai Zhao | 2016-02-23 |
| 9252146 | Work function adjustment by carbon implant in semiconductor devices including gate structure | Yue Liang, Dechao Guo, William K. Henson, Yanfeng Wang | 2016-02-02 |
| 9240482 | Asymmetric stressor DRAM | Ravi K. Dasaka, Ahmed Nayaz Noemaun, Karen A. Nummy, Katsunori Onishi, Paul C. Parries +3 more | 2016-01-19 |