Issued Patents 2016
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9443854 | FinFET with constrained source-drain epitaxial region | Arvind Kumar, Dan M. Mocuta | 2016-09-13 |
| 9437496 | Merged source drain epitaxy | Michael P. Chudzik, Edward P. Maciejewski, Kevin McStay, Shreesh Narasimha, Chengwen Pei +1 more | 2016-09-06 |
| 9379185 | Method of forming channel region dopant control in fin field effect transistor | Murshed Chowdhury, Arvind Kumar | 2016-06-28 |
| 9349609 | Semiconductor process temperature optimization | Yue Liang, Xiaojun Yu | 2016-05-24 |
| 9337338 | Tucked active region without dummy poly for performance boost and variation reduction | Yue Liang, Xiaojun Yu | 2016-05-10 |
| 9312274 | Merged fin structures for finFET devices | Andres Bryant, Jeffrey B. Johnson, Mickey H. Yu | 2016-04-12 |
| 9305999 | Stress-generating structure for semiconductor-on-insulator devices | Huilong Zhu, Dureseti Chidambarrao, Gregory G. Freeman | 2016-04-05 |
| 9299780 | Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device | Arvind Kumar, Dan M. Mocuta | 2016-03-29 |
| 9252215 | Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device | Arvind Kumar, Dan M. Mocuta | 2016-02-02 |