Issued Patents 2016
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9412840 | Sacrificial layer for replacement metal semiconductor alloy contact formation | Tenko Yamashita | 2016-08-09 |
| 9401583 | Laser structure on silicon using aspect ratio trapping growth | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2016-07-26 |
| 9395490 | Variable buried oxide thickness for a waveguide | Russell A. Budd, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana | 2016-07-19 |
| 9397005 | Dual-material mandrel for epitaxial crystal growth on silicon | Sanghoon Lee, Brent A. Wacaser | 2016-07-19 |
| 9397161 | Reduced current leakage semiconductor device | Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Yanning Sun | 2016-07-19 |
| 9391074 | Structure for FinFET fins | Tenko Yamashita | 2016-07-12 |
| 9373550 | Selectively degrading current resistance of field effect transistor devices | Veeraraghavan S. Basker, Dieter Wendel, Tenko Yamashita | 2016-06-21 |
| 9372307 | Monolithically integrated III-V optoelectronics with SI CMOS | Russell A. Budd, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana | 2016-06-21 |
| 9368569 | Punch through stopper for semiconductor device | Tenko Yamashita | 2016-06-14 |
| 9362177 | Nanowire semiconductor device | Wilfried Haensch, Tenko Yamashita | 2016-06-07 |
| 9362444 | Optoelectronics and CMOS integration on GOI substrate | Ning Li, Devendra K. Sadana | 2016-06-07 |
| 9362281 | Group III nitride integration with CMOS technology | Can Bayram, Christopher P. D'Emic, William J. Gallagher, Devendra K. Sadana | 2016-06-07 |
| 9355914 | Integrated circuit having dual material CMOS integration and method to fabricate same | — | 2016-05-31 |
| 9343325 | Trilayer SIT process with transfer layer for FINFET patterning | — | 2016-05-17 |
| 9337313 | Spacerless fin device with reduced parasitic resistance and capacitance and method to fabricate same | — | 2016-05-10 |
| 9337148 | Chip with programmable shelf life | — | 2016-05-10 |
| 9330984 | CMOS fin integration on SOI substrate | Tenko Yamashita | 2016-05-03 |
| 9331076 | Group III nitride integration with CMOS technology | Can Bayram, Christopher P. D'Emic, William J. Gallagher, Devendra K. Sadana | 2016-05-03 |
| 9324710 | Very planar gate cut post replacement gate process | — | 2016-04-26 |
| 9318492 | Floating body storage device employing a charge storage trench | — | 2016-04-19 |
| 9318392 | Method to form SOI fins on a bulk substrate with suspended anchoring | — | 2016-04-19 |
| 9318318 | 3D atomic layer gate or junction extender | Kevin K. Chan, Pouya Hashemi, Dae-Gyu Park, Min Yang | 2016-04-19 |
| 9305964 | Optoelectronic devices with back contact | Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana | 2016-04-05 |
| 9306038 | Shallow extension junction | Kevin K. Chan, Pouya Hashemi, Dae-Gyu Park, Min Yang | 2016-04-05 |
| 9299841 | Semiconductor devices and methods of manufacture | — | 2016-03-29 |