Issued Patents 2011
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8056038 | Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip | Kerim Kalafala, Hemlata Gupta, Jeffrey G. Hemmett | 2011-11-08 |
| 8056035 | Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz +2 more | 2011-11-08 |
| 8015526 | Static timing slacks analysis and modification | Thomas Chadwick, Margaret R. Charlebois, Jason Rotella, Douglas W. Stout, Ivan L. Wemple | 2011-09-06 |
| 7987440 | Method and system for efficient validation of clock skews during hierarchical static timing analysis | Kerim Kalafala, Jennifer E. Basile, Pooja M. Kotecha | 2011-07-26 |
| 7962874 | Method and system for evaluating timing in an integrated circuit | Eric A. Foreman, Peter A. Habitz, Jerry D. Hayes, Anthony D. Polson | 2011-06-14 |
| 7937604 | Method for generating a skew schedule for a clock distribution network containing gating elements | Revanta Banerji, Alex Rubin, Alexander J. Suess | 2011-05-03 |
| 7895556 | Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes | Pooja M. Kotecha, Louise H. Trevillyan | 2011-02-22 |
| 7890906 | Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells | Laura S. Chadwick, James A. Culp, Anthony D. Polson | 2011-02-15 |
| 7870525 | Slack sensitivity to parameter variation based timing analysis | Eric A. Foreman, Peter A. Habitz, Jerry D. Hayes, Jeffrey H. Oppold, Anthony D. Polson | 2011-01-11 |
| 7865861 | Method of generating wiring routes with matching delay in the presence of process variation | Peter A. Habitz, Jerry D. Hayes, Anthony D. Polson | 2011-01-04 |