Issued Patents 2011
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7996812 | Method of minimizing early-mode violations causing minimum impact to a chip design | Frank J. Musante, Veena S. Pureswaran, Louise H. Trevillyan, Paul G. Villarrubia | 2011-08-09 |
| 7987440 | Method and system for efficient validation of clock skews during hierarchical static timing analysis | Kerim Kalafala, Jennifer E. Basile, David J. Hathaway | 2011-07-26 |
| 7895556 | Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes | David J. Hathaway, Louise H. Trevillyan | 2011-02-22 |