Issued Patents 2011
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7962874 | Method and system for evaluating timing in an integrated circuit | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes | 2011-06-14 |
| 7890906 | Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells | Laura S. Chadwick, James A. Culp, David J. Hathaway | 2011-02-15 |
| 7877714 | System and method to optimize semiconductor power by integration of physical design timing and product performance measurements | Theodoros E. Anemikos, Jeanne P. Spence Bickford, Laura S. Chadwick, Susan K. Lichtensteiger | 2011-01-25 |
| 7870525 | Slack sensitivity to parameter variation based timing analysis | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold | 2011-01-11 |
| 7865861 | Method of generating wiring routes with matching delay in the presence of process variation | Peter A. Habitz, David J. Hathaway, Jerry D. Hayes | 2011-01-04 |