Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6967130 | Method of forming dual gate insulator layers for CMOS applications | Chi-Chun Chen, Tzu-Liang Lee | 2005-11-22 |
| 6936530 | Deposition method for Si-Ge epi layer on different intermediate substrates | Liang-Gi Yao, Kuen-Chyr Lee, Mong-Song Liang | 2005-08-30 |
| 6933157 | Semiconductor wafer manufacturing methods employing cleaning delay period | Chia-Lin Chen, Tze-Liang Lee | 2005-08-23 |
| 6914313 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Ming-Fang Wang, Chien-Hao Chen, Liang-Gi Yao | 2005-07-05 |
| 6911369 | Discontinuity prevention for SiGe deposition | Kuen-Chyr Lee, Liang-Gi Yao, Fu Chin Yang, Mong-Song Liang | 2005-06-28 |
| 6890811 | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices | Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao | 2005-05-10 |
| 6878610 | Relaxed silicon germanium substrate with low defect density | Chun Chich Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2005-04-12 |
| 6864109 | Method and system for determining a component concentration of an integrated circuit feature | Vincent S. Chang, Chi-Chun Chen, Chun-Lin Wu, Tze-Liang Lee | 2005-03-08 |
| 6861339 | Method for fabricating laminated silicon gate electrode | Chia-Lin Chen, Liang-Gi Yao | 2005-03-01 |