Issued Patents 2005
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979867 | SOI chip with mesa isolation and recess resistant regions | Hao Chen, Hsun-Chih Tsao, Fu-Liang Yang, Chenming Hu | 2005-12-27 |
| 6974755 | Isolation structure with nitrogen-containing liner and methods of manufacture | Chih-Hsin Ko, Chung-Hu Ge, Wen-Chin Lee | 2005-12-13 |
| 6955952 | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement | Chun-Chieh Lin, Fu-Liang Yang, Mong-Song Liang, Chenming Hu | 2005-10-18 |
| 6953972 | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer | Chun-Chieh Lin, Fu-Liang Yang, Chen Ming Hu | 2005-10-11 |
| 6949769 | Suppression of MOSFET gate leakage current | Chenming Hu | 2005-09-27 |
| 6949451 | SOI chip with recess-resistant buried insulator and method of manufacturing the same | Chenming Hu | 2005-09-27 |
| 6949443 | High performance semiconductor devices fabricated with strain-induced processes and methods for making same | Chung-Hu Ke, Wen-Chin Lee, Chih-Hsin Ko, Chenming Hu | 2005-09-27 |
| 6940705 | Capacitor with enhanced performance and method of manufacture | Chenming Hu | 2005-09-06 |
| 6936881 | Capacitor that includes high permittivity capacitor dielectric | Chenming Hu | 2005-08-30 |
| 6921913 | Strained-channel transistor structure with lattice-mismatched zone | Chun-Chieh Lin, Wen-Chin Lee, Chenming Hu | 2005-07-26 |
| 6911379 | Method of forming strained silicon on insulator substrate | Wen-Chin Lee | 2005-06-28 |
| 6906398 | Semiconductor chip with gate dielectrics for high-performance and low-leakage applications | Fu-Liang Yang, Chenming Hu | 2005-06-14 |
| 6905922 | Dual fully-silicided gate MOSFETs | Chuan-Yi Lin | 2005-06-14 |
| 6902962 | Silicon-on-insulator chip with multiple crystal orientations | Fu-Liang Yang | 2005-06-07 |
| 6882025 | Strained-channel transistor and methods of manufacture | Chih-Hsin Ko, Wen-Chin Lee, Chenming Hu | 2005-04-19 |
| 6879000 | Isolation for SOI chip with multiple silicon film thicknesses | — | 2005-04-12 |
| 6878610 | Relaxed silicon germanium substrate with low defect density | Chun Chich Lin, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang, Chenming Hu +4 more | 2005-04-12 |
| 6872606 | Semiconductor device with raised segment | Hao Chen, Fu-Liang Yang, Chenming Hu | 2005-03-29 |
| 6867433 | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors | How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang, Chenming Hu | 2005-03-15 |
| 6864519 | CMOS SRAM cell configured using multiple-gate transistors | Chenming Hu, Fu-Liang Yang | 2005-03-08 |
| 6864149 | SOI chip with mesa isolation and recess resistant regions | Hao Chen, Hsun-Chih Tsao, Fu-Liang Yang, Chenming Hu | 2005-03-08 |
| 6855606 | Semiconductor nano-rod devices | Hao Chen, Fu-Liang Yang, Chenming Hu | 2005-02-15 |
| 6855990 | Strained-channel multiple-gate transistor | Fu-Liang Yang, Chenming Hu | 2005-02-15 |
| 6844238 | Multiple-gate transistors with improved gate control | Fu-Liang Yang, Chenming Hu | 2005-01-18 |