Issued Patents 2005
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6936530 | Deposition method for Si-Ge epi layer on different intermediate substrates | Kuen-Chyr Lee, Shih-Chang Chen, Mong-Song Liang | 2005-08-30 |
| 6914313 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Ming-Fang Wang, Chien-Hao Chen, Shih-Chang Chen | 2005-07-05 |
| 6911369 | Discontinuity prevention for SiGe deposition | Kuen-Chyr Lee, Fu Chin Yang, Shih-Chang Chen, Mong-Song Liang | 2005-06-28 |
| 6890811 | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices | Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Shih-Chang Chen | 2005-05-10 |
| 6878610 | Relaxed silicon germanium substrate with low defect density | Chun Chich Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2005-04-12 |
| 6861339 | Method for fabricating laminated silicon gate electrode | Chia-Lin Chen, Shih-Chang Chen | 2005-03-01 |