Issued Patents 2005
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6974764 | Method for making a semiconductor device having a metal gate electrode | Justin K. Brask, Mark L. Doczy, Jack T. Kavalieros, Uday Shah, Matthew V. Metz +1 more | 2005-12-13 |
| 6974738 | Nonplanar device with stress incorporation layer and method of fabrication | Scott A. Hareland, Brian S. Doyle, Suman Datta | 2005-12-13 |
| 6974733 | Double-gate transistor with enhanced carrier mobility | Boyan Boyanov, Brian S. Doyle, Jack T. Kavalieros, Anand S. Murthy | 2005-12-13 |
| 6972228 | Method of forming an element of a microelectronic circuit | Brian S. Doyle, Anand S. Murthy | 2005-12-06 |
| 6970373 | Method and apparatus for improving stability of a 6T CMOS SRAM cell | Suman Datta, Brian S. Doyle, Jack T. Kavalieros, Bo Zheng, Scott A. Hareland | 2005-11-29 |
| 6952040 | Transistor structure and method of fabrication | Jack T. Kavalieros, Anand S. Murthy, Brian Roberds, Brian S. Doyle | 2005-10-04 |
| 6939815 | Method for making a semiconductor device having a high-k gate dielectric | Justin K. Brask, Mark L. Doczy, Scott A. Hareland, John Barnak, Matthew V. Metz +1 more | 2005-09-06 |
| 6933589 | Method of making a semiconductor transistor | Anand S. Murthy, Boyan Boyanov, Ravindra Soman | 2005-08-23 |
| 6914295 | Tri-gate devices and methods of fabrication | Brian S. Doyle, Jack T. Kavalieros, Douglas Barlage, Suman Datta, Scott A. Hareland | 2005-07-05 |
| 6909151 | Nonplanar device with stress incorporation layer and method of fabrication | Scott A. Hareland, Brian S. Doyle, Suman Datta, Been-Yih Jin | 2005-06-21 |
| 6900481 | Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors | Been-Yih Jin, Reza Arghavani | 2005-05-31 |
| 6897134 | Method for making a semiconductor device having a high-k gate dielectric | Justin K. Brask, Mark L. Doczy, John Barnak | 2005-05-24 |
| 6897098 | Method of fabricating an ultra-narrow channel semiconductor device | Scott A. Hareland | 2005-05-24 |
| 6893927 | Method for making a semiconductor device with a metal gate electrode | Uday Shah, Mark L. Doczy, Justin K. Brask, Jack T. Kavalieros, Matthew V. Metz | 2005-05-17 |
| 6890807 | Method for making a semiconductor device having a metal gate electrode | Mark L. Doczy, Markus Kuhn | 2005-05-10 |
| 6887800 | Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction | Matthew V. Metz, Suman Datta, Jack T. Kavalieros, Mark L. Doczy, Justin K. Brask +1 more | 2005-05-03 |
| 6887762 | Method of fabricating a field effect transistor structure with abrupt source/drain junctions | Anand S. Murthy, Patrick Morrow, Chia-Hong Jan, Paul Packan | 2005-05-03 |
| 6887395 | Method of forming sub-micron-size structures over a substrate | Scott A. Hareland, Brian S. Doyle | 2005-05-03 |
| 6885084 | Semiconductor transistor having a stressed channel | Anand S. Murthy, Tahir Ghani, Kaizad Mistry | 2005-04-26 |
| 6869889 | Etching metal carbide films | Justin K. Brask, Jack T. Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta +2 more | 2005-03-22 |
| 6864145 | Method of fabricating a robust gate dielectric using a replacement gate flow | Scott A. Hareland, Mark L. Doczy | 2005-03-08 |
| 6861318 | Semiconductor transistor having a stressed channel | Anand S. Murthy, Tahir Ghani, Kaizad Mistry | 2005-03-01 |
| 6858478 | Tri-gate devices and methods of fabrication | Brian S. Doyle, Jack T. Kavalieros, Douglas Barlage, Suman Datta, Scott A. Hareland | 2005-02-22 |