Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6974738 | Nonplanar device with stress incorporation layer and method of fabrication | Robert S. Chau, Brian S. Doyle, Suman Datta | 2005-12-13 |
| 6970373 | Method and apparatus for improving stability of a 6T CMOS SRAM cell | Suman Datta, Brian S. Doyle, Robert S. Chau, Jack T. Kavalieros, Bo Zheng | 2005-11-29 |
| 6939815 | Method for making a semiconductor device having a high-k gate dielectric | Justin K. Brask, Mark L. Doczy, John Barnak, Matthew V. Metz, Jack T. Kavalieros +1 more | 2005-09-06 |
| 6914295 | Tri-gate devices and methods of fabrication | Robert S. Chau, Brian S. Doyle, Jack T. Kavalieros, Douglas Barlage, Suman Datta | 2005-07-05 |
| 6909151 | Nonplanar device with stress incorporation layer and method of fabrication | Robert S. Chau, Brian S. Doyle, Suman Datta, Been-Yih Jin | 2005-06-21 |
| 6897098 | Method of fabricating an ultra-narrow channel semiconductor device | Robert S. Chau | 2005-05-24 |
| 6887395 | Method of forming sub-micron-size structures over a substrate | Brian S. Doyle, Robert S. Chau | 2005-05-03 |
| 6864145 | Method of fabricating a robust gate dielectric using a replacement gate flow | Mark L. Doczy, Robert S. Chau | 2005-03-08 |
| 6858478 | Tri-gate devices and methods of fabrication | Robert S. Chau, Brian S. Doyle, Jack T. Kavalieros, Douglas Barlage, Suman Datta | 2005-02-22 |