Issued Patents 2004
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6836166 | Method and system for delay control in synchronization circuits | Feng Lin, Brian Johnson | 2004-12-28 |
| 6819611 | Method and apparatus for data compression in memory devices | — | 2004-11-16 |
| 6806754 | Method and circuitry for reducing duty cycle distortion in differential delay lines | Ronnie M. Harrison | 2004-10-19 |
| 6807613 | Synchronized write data on a high speed memory bus | Brian Johnson | 2004-10-19 |
| 6807500 | Method and apparatus providing improved data path calibration for memory devices | Brian Johnson | 2004-10-19 |
| 6807114 | Method and system for selecting redundant rows and columns of memory cells | Troy A. Manning, Chris G. Martin, Ebrahim H. Hargan | 2004-10-19 |
| 6790732 | Self-aligned dual-gate transistor device and method of forming self-aligned dual-gate transistor device | John K. Zahurak, Charles H. Dennison | 2004-09-14 |
| 6762974 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM | Brian Johnson, Feng Lin | 2004-07-13 |
| 6757200 | Semiconductor memory having dual port cell supporting hidden refresh | Charles H. Dennison | 2004-06-29 |
| 6756836 | 256 Meg dynamic random access memory | Layne Bunker | 2004-06-29 |
| 6750700 | 256 meg dynamic random access memory | Layne Bunker, Scott J. Derner | 2004-06-15 |
| 6741104 | DRAM sense amplifier for low voltages | Leonard Forbes | 2004-05-25 |
| 6735102 | 256 Meg dynamic random access memory | Layne Bunker, Larry D. Kinsman | 2004-05-11 |
| 6724666 | Method of synchronizing read timing in a high speed memory system | Jeffery W. Janzen, Troy A. Manning, Chris G. Martin | 2004-04-20 |
| 6710631 | 256 Meg dynamic random access memory | Layne Bunker, Scott J. Derner | 2004-03-23 |
| 6710630 | 256 Meg dynamic random access memory | Layne Bunker | 2004-03-23 |
| 6703656 | Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in a 12″ wafer | Pierre C. Fazan | 2004-03-09 |
| 6697926 | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device | Brian Johnson, Troy A. Manning | 2004-02-24 |
| 6697297 | Apparatus for setting write latency | Brian Johnson | 2004-02-24 |
| 6696867 | Voltage generator with stability indicator circuit | Layne Bunker, Scott J. Derner | 2004-02-24 |
| 6696762 | Bi-level digit line architecture for high density DRAMS | — | 2004-02-24 |
| 6693836 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2004-02-17 |
| 6690609 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2004-02-10 |
| 6687185 | Method and apparatus for setting and compensating read latency in a high speed DRAM | Brian Johnson, Feng Lin | 2004-02-03 |
| 6686786 | Voltage generator stability indicator circuit | Layne Bunker, Scott J. Derner | 2004-02-03 |