Issued Patents 2004
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6807114 | Method and system for selecting redundant rows and columns of memory cells | Brent Keeth, Chris G. Martin, Ebrahim H. Hargan | 2004-10-19 |
| 6804743 | Two step memory device command buffer apparatus and method and memory devices and computer systems using same | — | 2004-10-12 |
| 6781397 | Electrical communication system for circuitry | — | 2004-08-24 |
| 6778453 | METHOD OF STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD OF MODIFYING OPERATION OF DYNAMIC RANDOM ACCESS MEMORY IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT | Christopher B. Cooper, Ming-Bo Liu, Chris G. Martin, Stephen L. Casper, Charles H. Dennison +3 more | 2004-08-17 |
| 6775755 | Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same | — | 2004-08-10 |
| 6757799 | Memory device with pipelined address path | Chris G. Martin | 2004-06-29 |
| 6728142 | Distributed write data drivers for burst access memories | Todd A. Merritt | 2004-04-27 |
| 6724666 | Method of synchronizing read timing in a high speed memory system | Jeffery W. Janzen, Chris G. Martin, Brent Keeth | 2004-04-20 |
| 6708262 | Memory device command signal generator | — | 2004-03-16 |
| 6697926 | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device | Brian Johnson, Brent Keeth | 2004-02-24 |
| 6693836 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Brian Johnson | 2004-02-17 |
| 6690609 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Brian Johnson | 2004-02-10 |
| 6683814 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Brian Johnson | 2004-01-27 |
| 6678205 | Multi-mode synchronous memory device and method of operating and testing same | Brian Johnson, Brent Keeth, Jeffrey W. Janzen, Chris G. Martin | 2004-01-13 |