Issued Patents 2004
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6834022 | Partial array self-refresh | Casey Kurth, Daryl L. Habersetzer | 2004-12-21 |
| 6816425 | Balanced sense amplifier control for open digit line architecture memory devices | Scot M. Graham, Stephen R. Porter | 2004-11-09 |
| 6788603 | ROM embedded DRAM with bias sensing | Casey Kurth, Phillip G. Wald | 2004-09-07 |
| 6785167 | ROM embedded DRAM with programming | Casey Kurth, Phillip G. Wald | 2004-08-31 |
| 6781867 | Embedded ROM device using substrate leakage | Casey Kurth, Phillip G. Wald | 2004-08-24 |
| 6771529 | ROM embedded DRAM with bias sensing | Casey Kurth, Phillip G. Wald | 2004-08-03 |
| 6768664 | ROM embedded DRAM with bias sensing | Casey Kurth, Phillip G. Wald | 2004-07-27 |
| 6750700 | 256 meg dynamic random access memory | Brent Keeth, Layne Bunker | 2004-06-15 |
| 6747889 | Half density ROM embedded DRAM | Casey Kurth, Phillip G. Wald | 2004-06-08 |
| 6735108 | ROM embedded DRAM with anti-fuse programming | Casey Kurth, Phillip G. Wald | 2004-05-11 |
| 6731556 | DRAM with bias sensing | Casey Kurth, Phillip G. Wald | 2004-05-04 |
| 6724238 | Antifuse circuit with improved gate oxide reliability | Casey Kurth | 2004-04-20 |
| 6717873 | Balanced sense amplifier control for open digit line architecture memory devices | Scot M. Graham, Stephen R. Porter | 2004-04-06 |
| 6710631 | 256 Meg dynamic random access memory | Brent Keeth, Layne Bunker | 2004-03-23 |
| 6696867 | Voltage generator with stability indicator circuit | Brent Keeth, Layne Bunker | 2004-02-24 |
| 6686786 | Voltage generator stability indicator circuit | Brent Keeth, Layne Bunker | 2004-02-03 |
| 6678186 | Row decoded biasing of sense amplifier for improved one's margin | Patrick J. Mullarkey | 2004-01-13 |
| 6674310 | 256 Meg dynamic random access memory | Brent Keeth, Layne Bunker | 2004-01-06 |