Issued Patents 2004
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6806754 | Method and circuitry for reducing duty cycle distortion in differential delay lines | Brent Keeth | 2004-10-19 |
| 6801989 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same | Brian Johnson | 2004-10-05 |
| 6781419 | Method and system for controlling the duty cycle of a clock signal | — | 2004-08-24 |
| 6777995 | Interlaced delay-locked loops for controlling memory-circuit timing | — | 2004-08-17 |
| 6753675 | Method and circuit for limiting a pumped voltage | — | 2004-06-22 |
| 6750639 | Method and circuit for limiting a pumped voltage | — | 2004-06-15 |
| 6744281 | Method and system for controlling the duty cycle of a clock signal | — | 2004-06-01 |
| 6690148 | Method and circuit for limiting a pumped voltage | — | 2004-02-10 |
| 6680874 | Delay lock loop circuit useful in a synchronous system and associated methods | — | 2004-01-20 |