Issued Patents 2003
Showing 26–50 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6593201 | Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods | — | 2003-07-15 |
| 6586792 | Structures, methods, and systems for ferroelectric memory transistors | Kie Y. Ahn | 2003-07-01 |
| 6586835 | Compact system module with built-in thermoelectric cooling | Kie Y. Ahn, Eugene H. Cloud | 2003-07-01 |
| 6586797 | Graded composition gate insulators to reduce tunneling barriers in flash memory devices | Jerome M. Eldridge | 2003-07-01 |
| 6580154 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction | Wendell P. Noble, Alan R. Reinberg | 2003-06-17 |
| 6574144 | Flash memory with nanocrystalline silicon film coating gate | — | 2003-06-03 |
| 6573169 | Highly conductive composite polysilicon gate for CMOS integrated circuits | Wendell P. Noble | 2003-06-03 |
| 6570248 | Structure and method for a high-performance electronic packaging assembly | Kie Y. Ahn, Eugene H. Cloud | 2003-05-27 |
| 6569715 | Large grain single crystal vertical thin film polysilicon mosfets | — | 2003-05-27 |
| 6566682 | Programmable memory address and decode circuits with ultra thin vertical body transistors | — | 2003-05-20 |
| 6566731 | Open pattern inductor | Kie Y. Ahn | 2003-05-20 |
| 6563345 | Monotonic dynamic static pseudo-NMOS logic circuits | — | 2003-05-13 |
| 6559491 | Folded bit line DRAM with ultra thin body transistors | Kie Y. Ahn | 2003-05-06 |
| 6556068 | Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits | Kie Y. Ahn | 2003-04-29 |
| 6552564 | Technique to reduce reflections and ringing on CMOS interconnections | Kie Y. Ahn | 2003-04-22 |
| 6552383 | Integrated decoupling capacitors | Kie Y. Ahn | 2003-04-22 |
| 6548107 | Methods of forming an insulating material proximate a substrate, and methods of forming an insulating material between components of an integrated circuit | Kie Y. Ahn | 2003-04-15 |
| 6545297 | High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown | Wendell P. Noble | 2003-04-08 |
| 6545314 | Memory using insulator traps | Joseph E. Geusic | 2003-04-08 |
| 6544846 | Method of manufacturing a single electron resistor memory device | Kie Y. Ahn | 2003-04-08 |
| 6541859 | Methods and structures for silver interconnections in integrated circuits | Paul A. Farrar, Kie Y. Ahn | 2003-04-01 |
| 6541362 | Methods of forming semiconductor structures | Kie Y. Ahn, Luan C. Tran | 2003-04-01 |
| 6538330 | Multilevel semiconductor-on-insulator structures and circuits | — | 2003-03-25 |
| 6539490 | Clock distribution without clock delay or skew | Kie Y. Ahn | 2003-03-25 |
| 6538476 | Method of forming a pseudo-differential current sense amplifier with hysteresis | — | 2003-03-25 |