Issued Patents 2003
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664173 | Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control | Mark L. Doczy, Pat Stokley | 2003-12-16 |
| 6656822 | Method for reduced capacitance interconnect system using gaseous implants into the ILD | Brian Roberds, Sandy Lee, Quat Vu | 2003-12-02 |
| 6653700 | Transistor structure and method of fabrication | Robert S. Chau, Jack T. Kavalieros, Anand S. Murthy, Brian Roberds | 2003-11-25 |
| 6638835 | Method for bonding and debonding films using a high-temperature polymer | Brian Roberds, Cindy Colinge | 2003-10-28 |
| 6624045 | Thermal conducting trench in a seminconductor structure and method for forming the same | Chunlin Liang | 2003-09-23 |
| 6605498 | Semiconductor transistor having a backfilled channel material | Anand S. Murthy, Brian Roberds | 2003-08-12 |
| 6596609 | Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer | Peng Cheng | 2003-07-22 |
| 6570220 | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition | Peng Cheng | 2003-05-27 |
| 6563152 | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel | Brian Roberds | 2003-05-13 |
| 6534837 | Semiconductor device | Gang Bai | 2003-03-18 |
| 6528856 | High dielectric constant metal oxide gate dielectrics | Gang Bai, David B. Fraser, Peng Cheng, Chunlin Liang | 2003-03-04 |