Issued Patents 2003
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664173 | Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control | Brian S. Doyle, Pat Stokley | 2003-12-16 |
| 6620713 | Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication | Reza Arghavani, Robert S. Chau, Brian Roberds | 2003-09-16 |
| 6617209 | Method for making a semiconductor device having a high-k gate dielectric | Robert S. Chau, Reza Arghavani | 2003-09-09 |