Issued Patents 2003
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6656822 | Method for reduced capacitance interconnect system using gaseous implants into the ILD | Brian S. Doyle, Sandy Lee, Quat Vu | 2003-12-02 |
| 6653700 | Transistor structure and method of fabrication | Robert S. Chau, Jack T. Kavalieros, Anand S. Murthy, Brian S. Doyle | 2003-11-25 |
| 6645828 | In situ plasma wafer bonding method | Sharon N. Farrens | 2003-11-11 |
| 6642133 | Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering | Doulgas Barlage | 2003-11-04 |
| 6638835 | Method for bonding and debonding films using a high-temperature polymer | Cindy Colinge, Brian S. Doyle | 2003-10-28 |
| 6620713 | Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication | Reza Arghavani, Robert S. Chau, Mark L. Doczy | 2003-09-16 |
| 6605498 | Semiconductor transistor having a backfilled channel material | Anand S. Murthy, Brian S. Doyle | 2003-08-12 |
| 6563152 | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel | Brian S. Doyle | 2003-05-13 |
| 6518109 | Technique to produce isolated junctions by forming an insulation layer | — | 2003-02-11 |