Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12021550 | Compression engine with configurable search depths and window sizes | Smita Kumar, Sailesh Bissessur, Stephen T. Palermo | 2024-06-25 |
| 11431351 | Selection of data compression technique based on input characteristics | Stephen T. Palermo, Sailesh Bissessur, Patrick Fleming, Lokpraveen Mosur, Smita Kumar +4 more | 2022-08-30 |
| 10680643 | Compression scheme with control of search agent activity | Stephen T. Palermo, Sailesh Bissessur, Patrick Fleming, Lokpraveen Mosur, Smita Kumar +4 more | 2020-06-09 |
| 10224957 | Hash-based data matching enhanced with backward matching for data compression | Christopher Cunningham | 2019-03-05 |
| 9830189 | Multi-threaded queuing system for pattern matching | Lokpraveen Mosur, Christopher P. Clark, Charles Arnold Lasswell | 2017-11-28 |
| 9223618 | Multi-threaded queuing system for pattern matching | Lokpraveen Mosur, Christopher F. Clark, Charles Arnold Lasswell | 2015-12-29 |
| 8705654 | Measuring phase shift in a radio frequency power amplifier | Nadim Khlat, Marcus Granger-Jones, Alexander Wayne Hietala | 2014-04-22 |
| 8370274 | Apparatuses and methods for deterministic pattern matching | Sanjeev Kumar Jain, Christopher F. Clark, Lokpraveen Mosur | 2013-02-05 |
| 7194766 | Method and system for high-speed processing IPSec security protocol packets | Lee Noehring, Chad W. Mercer, Michael Privett, Satish Anand | 2007-03-20 |
| 6385749 | Method and arrangement for controlling multiple test access port control modules | Swaroop Adusumilli, James Steele | 2002-05-07 |
| 6334198 | Method and arrangement for controlling multiply-activated test access port control modules | Swaroop Adusumilli, James Steele | 2001-12-25 |
| 6311302 | Method and arrangement for hierarchical control of multiple test access port control modules | James Steele, Swaroop Adusumilli | 2001-10-30 |
| 5842012 | Efficient soft reset in a personal computer | Gary Walker, Nicholas J. Richardson | 1998-11-24 |
| 5815675 | Method and apparatus for direct access to main memory by an I/O bus | James Steele, Barry Davis, Philip Wszolek, Brian Fall, Swaroop Adusumilli +2 more | 1998-09-29 |
| 5793992 | Method and apparatus for arbitrating access to main memory of a computer system | James Steele, Barry Davis, Philip Wszolek, Brian Fall, Swaroop Adusumilli +2 more | 1998-08-11 |
| 5794072 | Timing method and apparatus for interleaving PIO and DMA data transfers | Koichi Nomura, Gary D. Hicok, Franklyn H. Story | 1998-08-11 |
| 5781802 | First-in-first-out (FIFO) controller for buffering data between systems which are asynchronous and free of false flags and internal metastability | — | 1998-07-14 |
| 5752262 | System and method for enabling and disabling writeback cache | Philip Wszolek | 1998-05-12 |
| 5696938 | Computer system permitting mulitple write buffer read-arounds and method therefor | Timothy L. Wilson | 1997-12-09 |
| 5535360 | Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor | — | 1996-07-09 |