Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162788 | USB on the go (OTG) multi-hub endpoint reflector hub | Santosh Shetty, Pragash Mangalapandian, Lakshmi Narasimhan, Mark R. Bohm | 2018-12-25 |
| 10042784 | Side channel access through USB streams | Michael Simmons | 2018-08-07 |
| 7072996 | System and method of transferring data between a processing engine and a plurality of bus types using an arbiter | Satish Anand, Hemanshu Bhatnagar | 2006-07-04 |
| 6543018 | System and method to facilitate flexible control of bus drivers during scan test operations | Manoj Chandran | 2003-04-01 |
| 6438700 | System and method to reduce power consumption in advanced RISC machine (ARM) based systems | — | 2002-08-20 |
| 6418545 | System and method to reduce scan test pins on an integrated circuit | — | 2002-07-09 |
| 6412030 | System and method to optimize read performance while accepting write data in a PCI bus architecture | — | 2002-06-25 |
| 6385749 | Method and arrangement for controlling multiple test access port control modules | James Steele, David K. Cassetti | 2002-05-07 |
| 6334198 | Method and arrangement for controlling multiply-activated test access port control modules | James Steele, David K. Cassetti | 2001-12-25 |
| 6311302 | Method and arrangement for hierarchical control of multiple test access port control modules | David K. Cassetti, James Steele | 2001-10-30 |
| 6301631 | Memory mapping method for eliminating dual address cycles in a peripheral component interconnect environment | Peter Chambers, Subramanian S. Meiyappan | 2001-10-09 |
| 6289406 | Optimizing the performance of asynchronous bus bridges with dynamic transactions | Peter Chambers, Subramanian S. Meiyappan | 2001-09-11 |
| 6230216 | Method for eliminating dual address cycles in a peripheral component interconnect environment | Peter Chambers, Subramanian S. Meiyappan | 2001-05-08 |
| 6223232 | System and method to predict configuration of a bus target | Subramanian S. Meiyappan | 2001-04-24 |
| 6178478 | Smart target mechanism for eliminating dual address cycles in a peripheral component interconnect environment | Peter Chambers, Subramanian S. Meiyappan | 2001-01-23 |
| 5815675 | Method and apparatus for direct access to main memory by an I/O bus | James Steele, Barry Davis, Philip Wszolek, Brian Fall, David K. Cassetti +2 more | 1998-09-29 |
| 5793992 | Method and apparatus for arbitrating access to main memory of a computer system | James Steele, Barry Davis, Philip Wszolek, Brian Fall, David K. Cassetti +2 more | 1998-08-11 |
| 5761454 | Deadlock resolution methods and apparatus for interfacing concurrent and asynchronous buses | Barry Davis, Brian Fall, Nicholas J. Richardson, Philip Wszolek | 1998-06-02 |