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Driver for switched mode power supply |
John William Kesterson |
2025-01-14 |
| 11539294 |
Multi-level power converter with light load flying capacitor voltage regulation |
Aravind Mangudi, Mark Mercer, Taek Chang, Bill McKillop |
2022-12-27 |
| 10998818 |
Asynchronous dropout transition for multi-level and single-level buck converters |
John William Kesterson, Aravind Mangudi, Mark Mercer |
2021-05-04 |
| 6782466 |
Arrangement and method for accessing data in a virtual memory arrangement |
Desi Rhoden, George Crouse |
2004-08-24 |
| 6385749 |
Method and arrangement for controlling multiple test access port control modules |
Swaroop Adusumilli, David K. Cassetti |
2002-05-07 |
| 6334198 |
Method and arrangement for controlling multiply-activated test access port control modules |
Swaroop Adusumilli, David K. Cassetti |
2001-12-25 |
| 6311302 |
Method and arrangement for hierarchical control of multiple test access port control modules |
David K. Cassetti, Swaroop Adusumilli |
2001-10-30 |
| 5815675 |
Method and apparatus for direct access to main memory by an I/O bus |
Barry Davis, Philip Wszolek, Brian Fall, Swaroop Adusumilli, David K. Cassetti +2 more |
1998-09-29 |
| 5799178 |
System and method for starting and maintaining a central processing unit (CPU) clock using clock division emulation (CDE) during break events |
Gary Walker, Mike Crews |
1998-08-25 |
| 5793992 |
Method and apparatus for arbitrating access to main memory of a computer system |
Barry Davis, Philip Wszolek, Brian Fall, Swaroop Adusumilli, David K. Cassetti +2 more |
1998-08-11 |
| 5732226 |
Apparatus for granting either a CPU data bus or a memory data bus or a memory data bus access to a PCI bus |
Philip Wszolek, Rodney J. Pesavento, Brian Fall |
1998-03-24 |
| 5664213 |
Input/output (I/O) holdoff mechanism for use in a system where I/O device inputs are fed through a latency introducing bus |
Gary D. Hicok, David R. Evoy, Gary Walker, Joseph A. Thomsen, Lonnie C. Goff |
1997-09-02 |
