Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8565414 | Distributed VAD control system for telephone | Justin Allen, Seth Suppappola | 2013-10-22 |
| 7555117 | Path change detector for echo cancellation | Seth Suppappola | 2009-06-30 |
| 7295976 | Voice activity detector for telephone | Steven M. Domer, Justin Allen, Kellie Michele Vanda | 2007-11-13 |
| 7181767 | Keypad device security system and method | Rajeev Sethia, Mark Buer | 2007-02-20 |
| 6990194 | Dynamic balance control for telephone | James R. Mikesell | 2006-01-24 |
| 6928160 | Estimating bulk delay in a telephone system | Samuel Ponvarma Ebenezer | 2005-08-09 |
| 6658502 | Multi-channel and multi-modal direct memory access controller for optimizing performance of host bus | Subramanian S. Meiyappan | 2003-12-02 |
| 6560663 | Method and system for controlling internal busses to prevent bus contention during internal scan testing | Brian Logsdon, Ken Jaramillo, Subramanian S. Meiyappan | 2003-05-06 |
| 6523075 | Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource | Ken Jaramillo, Brian Logsdon, Subramanian S. Meiyappan | 2003-02-18 |
| 6434654 | System bus with a variable width selectivity configurable at initialization | Jerry Michael Rose, D. C. Sessions, Paul Reeves Auvil, III | 2002-08-13 |
| 6260092 | Point to point or ring connectable bus bridge and an interface with method for enhancing link performance in a point to point connectable bus bridge system using the fiber channel | Brian Logsdon, David Gerard Spaniol | 2001-07-10 |
| 6105142 | Intelligent power management interface for computer system hardware | Lonnie C. Goff, David R. Evoy, Mark Sullivan | 2000-08-15 |
| 5968144 | System for supporting DMA I/O device using PCI bus and PCI-PCI bridge comprising programmable DMA controller for request arbitration and storing data transfer information | Gary Walker, James J. Jirgal, Rishi Nalubola | 1999-10-19 |
| 5936976 | Selecting a test data input bus to supply test data to logical blocks within an integrated circuit | Koichi Nomura, Michael James Fickes | 1999-08-10 |
| 5933609 | Method and system for hot docking a portable computer to a docking station via the primary PCI bus | Gary Walker, David R. Evoy, Michael R. Crews, Peter Chambers | 1999-08-03 |
| 5930487 | PCI bus master with cascaded PCI arbitration | Omer Lem Wehunt, Jr. | 1999-07-27 |
| 5905912 | System for implementing peripheral device bus mastering in a computer using a list processor for asserting and receiving control signals external to the DMA controller | David R. Evoy, Peter Chambers, Lonnie C. Goff | 1999-05-18 |
| 5845151 | System using descriptor and having hardware state machine coupled to DMA for implementing peripheral device bus mastering via USB controller or IrDA controller | David R. Evoy, Peter Chambers, Lonnie C. Goff | 1998-12-01 |
| 5835791 | Versatile connection of a first keyboard/mouse interface and a second keyboard/mouse interface to a host computer | Lonnie C. Goff, David R. Evoy | 1998-11-10 |
| 5822548 | Programming interface for a universal asynchronous receiver/transmitter | Scott Harrow, Laura E. Simmons | 1998-10-13 |
| 5809333 | System for implementing peripheral device bus mastering in desktop PC via hardware state machine for programming DMA controller, generating command signals and receiving completion status | David R. Evoy, Peter Chambers, Lonnie C. Goff | 1998-09-15 |
| 5794072 | Timing method and apparatus for interleaving PIO and DMA data transfers | Koichi Nomura, Gary D. Hicok, David K. Cassetti | 1998-08-11 |
| 5774744 | System using DMA and descriptor for implementing peripheral device bus mastering via a universal serial bus controller or an infrared data association controller | David R. Evoy, Peter Chambers, Lonnie C. Goff | 1998-06-30 |
| 5774743 | System for implementing peripheral device bus mastering in mobile computer via micro-controller for programming DMA controller, generating and sending command signals, and receiving completion status | David R. Evoy, Peter Chambers, Lonnie C. Goff | 1998-06-30 |
| 5764933 | Deadlock prevention in a two bridge system by flushing write buffers in the first bridge | Nicholas J. Richardson, David R. Evoy | 1998-06-09 |