Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6785854 | Test access port (TAP) controller system and method to debug internal intermediate scan test faults | Prasad Vajjhala | 2004-08-31 |
| 6598104 | Smart retry system that reduces wasted bus transactions associated with master retries | Carl Knudsen | 2003-07-22 |
| 6560663 | Method and system for controlling internal busses to prevent bus contention during internal scan testing | Brian Logsdon, Franklyn H. Story, Subramanian S. Meiyappan | 2003-05-06 |
| 6523075 | Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource | Brian Logsdon, Franklyn H. Story, Subramanian S. Meiyappan | 2003-02-18 |
| 6397279 | Smart retry system that reduces wasted bus transactions associated with master retries | Carl Knudsen | 2002-05-28 |
| 6301632 | Direct memory access system and method to bridge PCI bus protocols and hitachi SH4 protocols | — | 2001-10-09 |
| 6178477 | Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource | Carl Knudsen | 2001-01-23 |
| 6073200 | System having processor monitoring capability of an integrated circuits buried, internal bus for use with a plurality of internal masters and a method therefor | Carl Knudsen | 2000-06-06 |
| 6016528 | Priority arbitration system providing low latency and guaranteed access for devices | David Gerard Spaniol | 2000-01-18 |
| 5884052 | Smart retry mechanism to program the retry latency of a PCI initiator agent | Peter Chambers | 1999-03-16 |