Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
KJ

Ken Jaramillo — 10 Patents

VTVlsi Technology: 6 patents #85 of 594Top 15%
Philips: 4 patents #1,244 of 7,731Top 20%
Phoenix, AZ: #643 of 6,660 inventorsTop 10%
Arizona: #3,693 of 32,909 inventorsTop 15%
Overall (All Time): #481,000 of 4,157,543Top 15%
10 Patents All Time
Ken Jaramillo has been granted 10 US patents while listed as an inventor at Vlsi Technology. The first was granted in 1999 and the most recent in August 2004. Ken Jaramillo ranks #481,000 of 4,157,543 US inventors in our database (top 11.6%). Patent records list Ken Jaramillo in Phoenix, AZ, US.

Patents per Year

Patents granted per year, 1999 to 2004Bar chart with a peak of 3 patents in 2003.peak 31999: 1 patents19992000: 2 patents20002001: 2 patents20012002: 1 patents20022003: 3 patents20032004: 1 patents2004

Issued Patents All Time

Showing 1–10 of 10 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6785854 Test access port (TAP) controller system and method to debug internal intermediate scan test faults Prasad Vajjhala 2004-08-31 $796,000
6598104 Smart retry system that reduces wasted bus transactions associated with master retries Carl Knudsen 2003-07-22 $1,129,000
6560663 Method and system for controlling internal busses to prevent bus contention during internal scan testing Brian Logsdon, Franklyn H. Story, Subramanian S. Meiyappan 2003-05-06 $1,096,000
6523075 Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource Brian Logsdon, Franklyn H. Story, Subramanian S. Meiyappan 2003-02-18 $1,310,000
6397279 Smart retry system that reduces wasted bus transactions associated with master retries Carl Knudsen 2002-05-28
6301632 Direct memory access system and method to bridge PCI bus protocols and hitachi SH4 protocols 2001-10-09
6178477 Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource Carl Knudsen 2001-01-23
6073200 System having processor monitoring capability of an integrated circuits buried, internal bus for use with a plurality of internal masters and a method therefor Carl Knudsen 2000-06-06
6016528 Priority arbitration system providing low latency and guaranteed access for devices David Gerard Spaniol 2000-01-18
5884052 Smart retry mechanism to program the retry latency of a PCI initiator agent Peter Chambers 1999-03-16 $3,261,000