Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10223493 | Dynamic tag allocation for clock reconvergence pessimism removal | — | 2019-03-05 |
| 9043771 | Software modification methods to provide master-slave execution for multi-processing and/or distributed parallel processing | Harsh Vardhan | 2015-05-26 |
| 8594988 | Method and apparatus for circuit simulation using parallel computing | Arnold Ginetti | 2013-11-26 |
| 7549134 | Method and system for performing crosstalk analysis | Jun Li, Hong Zhao, Hsien-Yen Chiu | 2009-06-16 |
| 7073140 | Method and system for performing crosstalk analysis | Jun Li, Hong Zhao, Hsien-Yen Chiu | 2006-07-04 |
| 5841672 | Method and apparatus for verifying signal timing of electrical circuits | Michael Grossman, Michael N. Misheloff, Thomas J. Schaefer, Marie C. Salet, Clementina Bures | 1998-11-24 |
| 5825658 | Method and a system for specifying and automatically analyzing multiple clock timing constraints in a VLSI circuit | Arnold Ginetti, Jean-Michel Fernandez, Francois Silve | 1998-10-20 |
| 5751596 | Automated system and method for identifying critical timing paths in integrated circuit layouts for use with automated circuit layout system | Arnold Ginetti | 1998-05-12 |
| 5608645 | Method of finding a critical path in a circuit by considering the clock skew | — | 1997-03-04 |
| 5555187 | Method and apparatus for determining the timing specification of a digital circuit | — | 1996-09-10 |