CB

Clementina Bures

VT Vlsi Technology: 1 patents #349 of 594Top 60%
Overall (All Time): #3,704,083 of 4,157,543Top 90%
1
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
5841672 Method and apparatus for verifying signal timing of electrical circuits Athanasius W. Spyrou, Michael Grossman, Michael N. Misheloff, Thomas J. Schaefer, Marie C. Salet 1998-11-24