| 10657302 |
Route generation and buffer placement for disjointed power domains in an integrated circuit |
Xavier Devyldere, Arnaud Pedenon |
2020-05-19 |
| 7810061 |
Method and system for creating a useful skew for an electronic circuit |
Salvatore D. Minonne, Thomas Menguy, Conor O'Sullivan |
2010-10-05 |
| 6836753 |
Cone slack allocator for computing time budgets |
— |
2004-12-28 |
| 6170080 |
Method and system for floorplanning a circuit design at a high level of abstraction |
Arnold Ginetti, Gerrard Tarroux, Jean-Michel Fernandes, Philippe Troin, Jean-Charles Giomi |
2001-01-02 |
| 6113647 |
Computer aided design system and method using hierarchical and flat netlist circuit representations |
Arnold Ginetti |
2000-09-05 |
| 6099584 |
System to fix post-layout timing and design rules violations |
Ginetti Arnold, Satish Raj |
2000-08-08 |
| 6086621 |
Logic synthesis constraints allocation automating the concurrent engineering flows |
Arnold Ginetti |
2000-07-11 |
| 5896299 |
Method and a system for fixing hold time violations in hierarchical designs |
Arnold Ginetti, Jean-Michel Fernandez |
1999-04-20 |
| 5825658 |
Method and a system for specifying and automatically analyzing multiple clock timing constraints in a VLSI circuit |
Arnold Ginetti, Athanasius W. Spyrou, Jean-Michel Fernandez |
1998-10-20 |
| 5764525 |
Method for improving the operation of a circuit through iterative substitutions and performance analyses of datapath cells |
Mossaddeq Mahmood, Balmukund K. Sharma, Arnold Ginetti |
1998-06-09 |
| 5633803 |
Process for the processing of specification data of logic functions of an application-specific integrated circuit |
Jean-Michel Fernandez, Arnold Ginetti |
1997-05-27 |