Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10192021 | Generating and inserting metal and metal etch shapes in a layout to correct design rule errors | Ying Wang, Joyjeet Bose, Sachin Shrivastava | 2019-01-29 |
| 9817941 | Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs | Jeffrey S. Salowe, Mark Rossman | 2017-11-14 |
| 9754072 | Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques | Jeffrey S. Salowe, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami | 2017-09-05 |
| 9384317 | Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques | Jeffrey S. Salowe, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami | 2016-07-05 |
| 9104830 | Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design | Jeffrey S. Salowe | 2015-08-11 |
| 8914763 | Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space | Supriya Ananthram | 2014-12-16 |
| 8910107 | Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space | Supriya Ananthram | 2014-12-09 |
| 8769467 | Method and system for utilizing hard and preferred rules for C-routing of electronic designs | David Chyan | 2014-07-01 |
| 8671368 | Method, system, and program product to implement detail routing for double pattern lithography | Jeffrey S. Salowe | 2014-03-11 |
| 8640080 | Method and system for visualizing pin access locations | Jeffrey S. Salowe | 2014-01-28 |
| 8560998 | Method, system, and program product to implement C-routing for double pattern lithography | Jeffrey S. Salowe | 2013-10-15 |
| 8375348 | Method, system, and program product to implement colored tiles for detail routing for double pattern lithography | Jeffrey S. Salowe | 2013-02-12 |
| 7752590 | Method and mechanism for implementing tessellation-based routing | David Chyan | 2010-07-06 |
| 7694261 | Method and mechanism for implementing tessellation-based routing | David Chyan | 2010-04-06 |
| 7222322 | Method and mechanism for implementing tessellation-based routing | David Chyan | 2007-05-22 |
| 6601226 | Tightloop method of timing driven placement | Dwight D. Hill | 2003-07-29 |
| 6099584 | System to fix post-layout timing and design rules violations | Ginetti Arnold, Francois Silve | 2000-08-08 |