Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10049175 | Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns | Min Cao, Roland Ruehl, Jeffrey Markham | 2018-08-14 |
| 9817941 | Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs | Satish Raj, Mark Rossman | 2017-11-14 |
| 9754072 | Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques | Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami | 2017-09-05 |
| 9384317 | Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques | Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami | 2016-07-05 |
| 9251299 | Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs | — | 2016-02-02 |
| 9213793 | Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks | — | 2015-12-15 |
| 9183343 | Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs | Viral Mankad, Supriya Ananthram | 2015-11-10 |
| 9165103 | Methods, systems, and articles of manufacture for tessellating and labeling routing space for routing electronic designs | — | 2015-10-20 |
| 9117052 | Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns | Min Cao, Roland Ruehl, Jeffrey Markham | 2015-08-25 |
| 9104830 | Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design | Satish Raj | 2015-08-11 |
| 9075932 | Methods and systems for routing an electronic design using spacetiles | — | 2015-07-07 |
| 9003349 | Methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks | — | 2015-04-07 |
| 8984465 | Methods, systems, and articles of manufacture for automatically assigning track patterns to regions for physical implementation of an electronic design | — | 2015-03-17 |
| 8935649 | Methods, systems, and articles of manufacture for routing an electronic design using spacetiles | — | 2015-01-13 |
| 8671368 | Method, system, and program product to implement detail routing for double pattern lithography | Satish Raj | 2014-03-11 |
| 8640080 | Method and system for visualizing pin access locations | Satish Raj | 2014-01-28 |
| 8560998 | Method, system, and program product to implement C-routing for double pattern lithography | Satish Raj | 2013-10-15 |
| 8375348 | Method, system, and program product to implement colored tiles for detail routing for double pattern lithography | Satish Raj | 2013-02-12 |
| 8117569 | Method and mechanism for implementing a minimum spanning tree | — | 2012-02-14 |
| 8065652 | Method and system for determining hard and preferred rules in global routing of electronic designs | Charles T. Houck | 2011-11-22 |
| 7676781 | Method and mechanism for implementing a minimum spanning tree | — | 2010-03-09 |
| 7594214 | Maximum flow analysis for electronic circuit design | Steven Lee Pucci | 2009-09-22 |
| 7100129 | Hierarchical gcell method and mechanism | Eric Nequist | 2006-08-29 |
| 7100128 | Zone tree method and mechanism | Eric Nequist, Steven Lee Pucci | 2006-08-29 |
| 7089526 | Maximum flow analysis for electronic circuit design | Steven Lee Pucci | 2006-08-08 |