JF

Jean-Michel Fernandez

VT Vlsi Technology: 3 patents #168 of 594Top 30%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
CS Candence Design Systems: 1 patents #1 of 20Top 5%
Overall (All Time): #1,029,928 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
7359846 Modeling an ASIC based on static pipeline delays 2008-04-15
6397370 Method and system for breaking complex Boolean networks Gerard Tarroux 2002-05-28
5896299 Method and a system for fixing hold time violations in hierarchical designs Arnold Ginetti, Francois Silve 1999-04-20
5825658 Method and a system for specifying and automatically analyzing multiple clock timing constraints in a VLSI circuit Arnold Ginetti, Athanasius W. Spyrou, Francois Silve 1998-10-20
5633803 Process for the processing of specification data of logic functions of an application-specific integrated circuit Francois Silve, Arnold Ginetti 1997-05-27