Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10020043 | Methods of reading and writing data in a thyristor random access memory | Harry Luan, Valery Axelrad, Charlie Cheng | 2018-07-10 |
| 10020308 | Thyristor memory cell with assist device | Harry Luan, Valery Axelrad, Charlie Cheng | 2018-07-10 |
| 9899389 | Two-transistor SRAM semiconductor structure and methods of fabrication | Harry Luan, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier | 2018-02-20 |
| 9870823 | Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations | Chang Hua Siau | 2018-01-16 |
| 9842639 | Systems and methods for managing read voltages in a cross-point memory array | Frank Guo | 2017-12-12 |
| 9837418 | Thyristor volatile random access memory and methods of manufacture | Harry Luan, Valery Axelrad, Charlie Cheng | 2017-12-05 |
| 9837149 | Low read current architecture for memory | Christophe J. Chevallier, Darrell Rinerson, Chang Hua Siau | 2017-12-05 |
| 9748223 | Six-transistor SRAM semiconductor structures and methods of fabrication | Harry Luan, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier | 2017-08-29 |
| 9741413 | Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells | Harry Luan, Valery Axelrad, Charlie Cheng | 2017-08-22 |
| 9691821 | Vertical cross-point arrays for ultra-high-density memory applications | — | 2017-06-27 |
| 9691480 | Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations | Chang Hua Siau | 2017-06-27 |
| 9653151 | Memory array having segmented row addressed page registers | Adrian E. Ong | 2017-05-16 |
| 9613968 | Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication | Harry Luan, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier | 2017-04-04 |
| 9570459 | Vertical gate NAND memory devices | — | 2017-02-14 |
| 9564198 | Six-transistor SRAM semiconductor structures and methods of fabrication | Harry Luan, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier | 2017-02-07 |
| 9564199 | Methods of reading and writing data in a thyristor random access memory | Harry Luan, Valery Axelrad, Charlie Cheng | 2017-02-07 |
| 9564441 | Two-transistor SRAM semiconductor structure and methods of fabrication | Harry Luan, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier | 2017-02-07 |
| 9530482 | Methods of retaining and refreshing data in a thyristor random access memory | Harry Luan, Valery Axelrad, Charlie Cheng | 2016-12-27 |
| 9496020 | Six-transistor thyristor SRAM circuits and methods of operation | Harry Luan, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier | 2016-11-15 |
| 9496021 | Power reduction in thyristor random access memory | Harry Luan, Valery Axelrad, Charlie Cheng | 2016-11-15 |
| 9460771 | Two-transistor thyristor SRAM circuit and methods of operation | Harry Luan, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier | 2016-10-04 |
| 9449669 | Cross-coupled thyristor SRAM circuits and methods of operation | Harry Luan, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier | 2016-09-20 |
| 9437291 | Distributed cascode current source for RRAM set current limitation | — | 2016-09-06 |
| 9419217 | Vertical cross-point memory arrays | Lidia Vereen, David Eggleston, Louis C. Parrillo | 2016-08-16 |
| 9390796 | Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations | Chang Hua Siau | 2016-07-12 |