Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8772904 | Semiconductor structure and process thereof | Chih-Chien Liu, Chia-Lung Chang, Jui-Min Lee, Yuh-Min Lin | 2014-07-08 |
| 8709901 | Method of forming an isolation structure | Chia-Lung Chang, Wu-Sian Sie, Wen-Yi Teng, Chih-Chien Liu, Jui-Min Lee +1 more | 2014-04-29 |
| 8692332 | Strained-silicon transistor and method of making the same | Hsiu-Lien Liao, Yu-Tuan Tsai, Teng-Chun Tsai | 2014-04-08 |
| 8674452 | Semiconductor device with lower metal layer thickness in PMOS region | Chin-Cheng Chien, Tzung-Ying Lee, Tsuo-Wen Lu, Shu-Yen Chan, Yu-Min Lin +1 more | 2014-03-18 |
| 8580625 | Metal oxide semiconductor transistor and method of manufacturing the same | Tsuo-Wen Lu, Tzung-Ying Lee, Chun-Wei Hsu, Yu-Min Lin, Chia-Lung Chang +2 more | 2013-11-12 |
| 8536038 | Manufacturing method for metal gate using ion implantation | Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu +8 more | 2013-09-17 |
| 7514347 | Interconnect structure and fabricating method thereof | Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Shu-Jen Sung | 2009-04-07 |
| 7439154 | Method of fabricating interconnect structure | Feng-Yu Hsu, Chih-Chien Liu, Jim-Jey Huang | 2008-10-21 |
| 7378343 | Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content | Miao-Chun Lin, Kuo-Chih Lai, Mei-Ling Chen, Cheng-Ming Weng, Chun-Jen Huang +1 more | 2008-05-27 |
| 6960522 | Method for making damascene interconnect with bilayer capping film | Yi-Fang Chiang, Chih-Chien Liu | 2005-11-01 |
| 6873057 | Damascene interconnect with bi-layer capping film | Yi-Fang Chiang, Chih-Chien Liu | 2005-03-29 |