Issued Patents All Time
Showing 176–200 of 222 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5460999 | Method for making fin-shaped stack capacitors on DRAM chips | Chen-Chiu Hsue | 1995-10-24 |
| 5457061 | Method of making top floating-gate flash EEPROM structure | Chen-Chiu Hsue | 1995-10-10 |
| 5453635 | Lightly doped drain transistor device having the polysilicon sidewall spacers | Chen-Chung Hsu | 1995-09-26 |
| 5453392 | Process for forming flat-cell mask ROMS | Chen-Chiu Hsue | 1995-09-26 |
| 5449644 | Process for contact hole formation using a sacrificial SOG layer | Cheng-Han Huang, Ming-Tzong Yang, Hong-Tsz Pan | 1995-09-12 |
| 5449632 | Mask ROM process with self-aligned ROM code implant | — | 1995-09-12 |
| 5449638 | Process on thickness control for silicon-on-insulator technology | Chen-Chiu Hsue, H. J. Wu, Lawrence Lin | 1995-09-12 |
| 5445983 | Method of manufacturing EEPROM memory device with a select gate | — | 1995-08-29 |
| 5445984 | Method of making a split gate flash memory cell | Hwi-Huang Chen | 1995-08-29 |
| 5438009 | Method of fabrication of MOSFET device with buried bit line | Ming-Tzong Yang | 1995-08-01 |
| 5436185 | Method of fabricating a ROM device with a negative code implant mask | Chen-Chiu Hsue | 1995-07-25 |
| 5436186 | Process for fabricating a stacked capacitor | Chen-Chiu Hsue, Ming-Tzong Yang | 1995-07-25 |
| 5432112 | Process for EPROM, flash memory with high coupling ratio | — | 1995-07-11 |
| 5432106 | Manufacture of an asymmetric non-volatile memory cell | — | 1995-07-11 |
| 5429956 | Method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel | Yau-Kae Shell | 1995-07-04 |
| 5429960 | Method of making flash EEPROM memory | — | 1995-07-04 |
| 5429967 | Process for producing a very high density mask ROM | — | 1995-07-04 |
| 5429970 | Method of making flash EEPROM memory cell | — | 1995-07-04 |
| 5429973 | Trench buried-bit line mask ROM process | — | 1995-07-04 |
| 5429976 | Self-aligned method for forming polysilicon word lines on top of gate electrodes to increase capacitance of a stacked capacitor in a DRAM cell | Cheng-Han Huang | 1995-07-04 |
| 5430673 | Buried bit line ROM with low bit line resistance | Chen-Chiu Hsue | 1995-07-04 |
| 5427968 | Split-gate flash memory cell with separated and self-aligned tunneling regions | — | 1995-06-27 |
| 5427970 | Method of making flash memory with high coupling ratio | Chen-Chih Hsue | 1995-06-27 |
| 5422292 | Process for fabricating split gate flash EEPROM memory | Hwi-Huang Chen, Yau-Kae Sheu | 1995-06-06 |
| 5418175 | Process for flat-cell mask ROM integrated circuit | Chen-Chiu Hsue | 1995-05-23 |