Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9001443 | Method and system for testing a controller of a hard disk drive | Lim Hudiono | 2015-04-07 |
| 8638512 | Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive | Lim Hudiono | 2014-01-28 |
| 8270107 | Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive | Lim Hudiono | 2012-09-18 |
| 8031422 | Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive | Lim Hudiono | 2011-10-04 |
| 7836379 | Method for computing buffer ECC | Mohammad M. Negahban, Yujun Si | 2010-11-16 |
| 7813067 | Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive | Lim Hudiono | 2010-10-12 |
| 7559009 | System and method for performing parity checks in disk storage systems | — | 2009-07-07 |
| 7543214 | Method and system for performing CRC | — | 2009-06-02 |
| 7111228 | System and method for performing parity checks in disk storage system | — | 2006-09-19 |
| 7080188 | Method and system for embedded disk controllers | Larry L. Byers, Joseph G. Kriscunas, Joseba M. Desubijana, Gary R. Robeck, Michael R. Spaur +1 more | 2006-07-18 |
| 5809533 | Dual bus system with multiple processors having data coherency maintenance | Dan T. Tran, Jayesh V. Sheth, Theodore C. White, Richard A. Cowgill | 1998-09-15 |
| 5553259 | Apparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registers | David Kalish, Saul Barajas | 1996-09-03 |
| 5553263 | Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory | David Kalish, Saul Barajas | 1996-09-03 |
| 5511224 | Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories | Dan T. Tran, Jayesh V. Sheth, Theodore C. White, Richard A. Cowgill | 1996-04-23 |
| 5509127 | Transmission logic apparatus for dual bus network | Wayne C. Datwyler | 1996-04-16 |
| 5495585 | Programmable timing logic system for dual bus interface | Wayne C. Datwyler | 1996-02-27 |
| 5444860 | Translator system for message transfers between digital units operating on different message protocols and different clock rates | Wayne C. Datwyler | 1995-08-22 |
| 5442754 | Receiving control logic system for dual bus network | Wayne C. Datwyler | 1995-08-15 |
| 5404462 | Dual bus interface transfer system for central processing module | Wayne C. Datwyler | 1995-04-04 |
| 5293496 | Inhibit write apparatus and method for preventing bus lockout | Theodore C. White, Jayesh V. Sheth, Dan T. Tran | 1994-03-08 |
| 5293621 | Varying wait interval retry apparatus and method for preventing bus lockout | Theodore C. White, Jayesh V. Sheth, Dan T. Tran | 1994-03-08 |