Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5809533 | Dual bus system with multiple processors having data coherency maintenance | Dan T. Tran, Paul B. Ricci, Jayesh V. Sheth, Theodore C. White | 1998-09-15 |
| 5511224 | Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories | Dan T. Tran, Paul B. Ricci, Jayesh V. Sheth, Theodore C. White | 1996-04-23 |
| 5386517 | Dual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O devices with varying transfer speeds | Jayesh V. Sheth, Craig W. Harris, Theodore C. White, Kha Nguyen, Chung W. Wong | 1995-01-31 |
| 5113500 | Multiple cooperating and concurrently operating processors using individually dedicated memories | Jefferson F. Talbott, Chris Cummings, James Albert Fontana, Anthony Reginald Pitchford | 1992-05-12 |