Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6070166 | Apparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bit | Bruce Ernest Whittaker, Donald M. Kalish | 2000-05-30 |
| 5991853 | Methods for accessing coincident cache with a bit-sliced architecture | Bruce Ernest Whittaker, Donald M. Kalish | 1999-11-23 |
| 5689680 | Cache memory system and method for accessing a coincident cache with a bit-sliced architecture | Bruce Ernest Whittaker, David Kalish | 1997-11-18 |
| 5642486 | "Invalidation queue with ""bit-sliceability""" | Bruce Ernest Whittaker, David Kalish | 1997-06-24 |
| 5598551 | Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles | David Kalish, Bruce Ernest Whittaker, Keith S. Saldanha | 1997-01-28 |
| 5561773 | Programmable, multi-purpose virtual pin multiplier | David Kalish, Bruce Ernest Whittaker | 1996-10-01 |
| 5553259 | Apparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registers | David Kalish, Paul B. Ricci | 1996-09-03 |
| 5553263 | Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory | David Kalish, Paul B. Ricci | 1996-09-03 |
| 5506967 | Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures | David Kalish, Bruce Ernest Whittaker | 1996-04-09 |
| 5459836 | Inter-processor communication net | Bruce Ernest Whittaker, Leland E. Watson | 1995-10-17 |
| 5418935 | Apparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is received | Bruce Ernest Whittaker, Leland E. Watson | 1995-05-23 |
| 5321814 | System for optional module detection and reconfiguration | Leland E. Watson, Bruce Ernest Whittaker | 1994-06-14 |
| 5146596 | Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests | Bruce Ernest Whittaker, Leland E. Watson | 1992-09-08 |
| 5117132 | Flexible utilization of general flip-flops in programmable array logic | Leland E. Watson, Bruce Ernest Whittaker | 1992-05-26 |
| 5087839 | Method of providing flexibility and alterability in VLSI gate array chips | Bruce Ernest Whittaker | 1992-02-11 |
| 5087953 | Flexible gate array system for combinatorial logic | Bruce Ernest Whittaker | 1992-02-11 |
| 5086427 | Clocked logic circuitry preventing double driving on shared data bus | Bruce Ernest Whittaker, Leland E. Watson | 1992-02-04 |