Issued Patents All Time
Showing 1–25 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7793229 | Recording relevant information in a GUI window of a panel dump browser tool | Leland E. Watson | 2010-09-07 |
| 7401261 | Automatic analysis of memory operations using panel dump file | Leland E. Watson | 2008-07-15 |
| 7171593 | Displaying abnormal and error conditions in system state analysis | Leland E. Watson, Scott L. Brock, Stephanie Ninh Truong | 2007-01-30 |
| 6295563 | Control system for recreating of data output clock frequency which matches data input clock frequency during data transferring | — | 2001-09-25 |
| 6070166 | Apparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bit | Donald M. Kalish, Saul Barajas | 2000-05-30 |
| 6070233 | Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache | — | 2000-05-30 |
| 6041337 | Linear function generator method with counter for implementation of control signals in digital logic | — | 2000-03-21 |
| 6000015 | Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache | — | 1999-12-07 |
| 5991853 | Methods for accessing coincident cache with a bit-sliced architecture | Donald M. Kalish, Saul Barajas | 1999-11-23 |
| 5935200 | Exponential functional relationship generator method and system for implementation in digital logic | — | 1999-08-10 |
| 5928310 | Digital device control method and system via linear function generator implementation using adder for intercept | — | 1999-07-27 |
| 5889959 | Fast write initialization method and system for loading channel adapter microcode | James H. Jeppesen, III | 1999-03-30 |
| 5850513 | Processor path emulation system providing fast readout and verification of main memory by maintenance controller interface to maintenance subsystem | James H. Jeppesen, III | 1998-12-15 |
| 5832250 | Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits | — | 1998-11-03 |
| 5822334 | High speed initialization system for RAM devices using JTAG loop for providing valid parity bits | James H. Jeppesen, III | 1998-10-13 |
| 5790813 | Pre-arbitration system allowing look-around and bypass for significant operations | — | 1998-08-04 |
| 5768299 | Derived generation system for parity bits with bi-directional, crossed-fields utilizing stored flip-bit feature | — | 1998-06-16 |
| 5737567 | Fast write initialization system for microcode RAM via data path array using pre-loaded flash memory an programmable control logic array | James H. Jeppesen, III | 1998-04-07 |
| 5729712 | Smart fill system for multiple cache network | — | 1998-03-17 |
| 5717872 | Flexible, soft, random-like counter system for bus protocol waiting periods | — | 1998-02-10 |
| 5717900 | Adjusting priority cache access operations with multiple level priority states between a central processor and an invalidation queue | — | 1998-02-10 |
| 5706297 | System for adapting maintenance operations to JTAG and non-JTAG modules | James H. Jeppesen, III | 1998-01-06 |
| 5706424 | System for fast read and verification of microcode RAM | James H. Jeppesen, III | 1998-01-06 |
| 5701431 | Method and system for randomly selecting a cache set for cache fill operations | — | 1997-12-23 |
| 5699552 | System for improved processor throughput with enhanced cache utilization using specialized interleaving operations | — | 1997-12-16 |