Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5689680 | Cache memory system and method for accessing a coincident cache with a bit-sliced architecture | David Kalish, Saul Barajas | 1997-11-18 |
| 5687348 | Variable-depth, self-regulating cache queue flushing system | — | 1997-11-11 |
| 5666513 | Automatic reconfiguration of multiple-way cache system allowing uninterrupted continuing processor operation | — | 1997-09-09 |
| 5642486 | "Invalidation queue with ""bit-sliceability""" | David Kalish, Saul Barajas | 1997-06-24 |
| 5640531 | Enhanced computer operational system using auxiliary mini-cache for enhancement to general cache | Leland E. Watson | 1997-06-17 |
| 5598551 | Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles | Saul Barajas, David Kalish, Keith S. Saldanha | 1997-01-28 |
| 5561773 | Programmable, multi-purpose virtual pin multiplier | David Kalish, Saul Barajas | 1996-10-01 |
| 5537609 | Mini cache operational module for enhancement to general cache | Leland E. Watson | 1996-07-16 |
| 5530727 | Half synchronizer circuit interface system | James H. Jeppesen, III | 1996-06-25 |
| 5506967 | Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures | Saul Barajas, David Kalish | 1996-04-09 |
| 5459836 | Inter-processor communication net | Saul Barajas, Leland E. Watson | 1995-10-17 |
| 5418935 | Apparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is received | Saul Barajas, Leland E. Watson | 1995-05-23 |
| 5355468 | System for halting synchronous digital modules | James H. Jeppesen, III | 1994-10-11 |
| 5321814 | System for optional module detection and reconfiguration | Saul Barajas, Leland E. Watson | 1994-06-14 |
| 5146596 | Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests | Saul Barajas, Leland E. Watson | 1992-09-08 |
| 5117132 | Flexible utilization of general flip-flops in programmable array logic | Leland E. Watson, Saul Barajas | 1992-05-26 |
| 5117428 | System for memory data integrity | James H. Jeppesen, III | 1992-05-26 |
| 5087839 | Method of providing flexibility and alterability in VLSI gate array chips | Saul Barajas | 1992-02-11 |
| 5087953 | Flexible gate array system for combinatorial logic | Saul Barajas | 1992-02-11 |
| 5088092 | Width-expansible memory integrity structure | James H. Jeppesen, III | 1992-02-11 |
| 5086427 | Clocked logic circuitry preventing double driving on shared data bus | Saul Barajas, Leland E. Watson | 1992-02-04 |
| 5052001 | Multiple memory bank parity checking system | James H. Jeppesen, III | 1991-09-24 |
| 4677566 | Power control network for multiple digital modules | James H. Jeppesen, III, Larry D. Sharp | 1987-06-30 |
| 4658353 | System control network for multiple processor modules | James H. Jeppesen, III, Andrew Ward Beale | 1987-04-14 |
| 4635195 | Power control network using reliable communications protocol | James H. Jeppesen, III | 1987-01-06 |