Issued Patents All Time
Showing 26–50 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5519876 | Processor communications bus having address lines selecting different storage locations based on selected control lines | Joseba M. De Subijana, Wayne A. Michaelson | 1996-05-21 |
| 5515501 | Redundant maintenance architecture | Paul A. LaBerge, Greg Wiedenman | 1996-05-07 |
| 5515507 | Multiple width data bus for a microsequencer bus controller system | Joseba M. De Subijana, Wayne A. Michaelson, Lloyd E. Thorsbakken, Howard Huy P. Tran | 1996-05-07 |
| 5511164 | Method and apparatus for determining the source and nature of an error within a computer system | Terry J. Brunmeier, John A. Miller, Gary R. Robeck | 1996-04-23 |
| 5495589 | Architecture for smart control of bi-directional transfer of data | Donald W. Mackenthun, Gregory B. Wiedenman, Ferris T. Price, deceased | 1996-02-27 |
| 5495598 | Stuck fault detection for branch instruction condition signals | Joseba M. De Subijana, Wayne A. Michaelson | 1996-02-27 |
| 5488702 | Data block check sequence generation and validation in a file cache system | Joseba M. Desubijana, Wayne A. Michaelson | 1996-01-30 |
| 5487159 | System for processing shift, mask, and merge operations in one instruction | Joseba M. De Subijana, Wayne A. Michaelson | 1996-01-23 |
| 5475815 | Built-in-self-test scheme for testing multiple memory elements | Aaron C. Peterson, Joseph G. Kriscunas, Gerald J. Maciona, Jeff Engel | 1995-12-12 |
| 5471482 | VLSI embedded RAM test | Donald W. Mackenthun, Philip J. Fye, Gerald J. Maciona, Jeff Engel, Ferris T. Price, deceased +1 more | 1995-11-28 |
| 5471597 | System and method for executing branch instructions wherein branch target addresses are dynamically selectable under programmer control from writable branch address tables | Joseba M. De Subijana, Wayne A. Michaelson | 1995-11-28 |
| 5434818 | Four port RAM cell | Duane G. Kurth, Ashgar K. Malik | 1995-07-18 |
| 5423030 | Bus station abort detection | Joseba M. Desubijana, Wayne A. Michaelson | 1995-06-06 |
| 5422915 | Fault tolerant clock distribution system | Thomas T. Kubista, Gregory B. Wiedenman | 1995-06-06 |
| 5416362 | Transparent flip-flop | Fernando W. Arraut, Dale K. Seppa | 1995-05-16 |
| 5394443 | Multiple interval single phase clock | Randy L. DeGarmo | 1995-02-28 |
| 5257382 | Data bank priority system | Wayne A. Michaelson, Howard A. Koehler | 1993-10-26 |
| 5168555 | Initial program load control | Joseba M. Desubijana | 1992-12-01 |
| 5142629 | System for interconnecting MSUs to a computer system | Joseba M. Desubijana | 1992-08-25 |
| 5060145 | Memory access system for pipelined data paths to and from storage | James H. Scheuneman, Wayne A. Michaelson | 1991-10-22 |
| 5032984 | Data bank priority system | Howard A. Koehler, Wayne A. Michaelson | 1991-07-16 |
| 4996688 | Fault capture/fault injection system | Kay Tsang, James H. Scheuneman, Penny L. Svenkeson | 1991-02-26 |
| 4962501 | Bus data transmission verification system | James H. Scheuneman, Joseba M. Desubijana | 1990-10-09 |
| 4953131 | Unconditional clock and automatic refresh logic | David M. Purdham, James H. Scheuneman, Terence Sych, Kwisook Tsang | 1990-08-28 |
| 4953167 | Data bus enable verification logic | Wayne A. Michaelson, Joseba M. Desubijana | 1990-08-28 |