JS

James H. Scheuneman

UN Unisys: 12 patents #63 of 2,015Top 4%
SP Sperry: 8 patents #22 of 841Top 3%
Overall (All Time): #226,702 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
5068782 Accessing control with predetermined priority based on a feedback arrangement Lawrence R. Fontaine 1991-11-26
5060145 Memory access system for pipelined data paths to and from storage Larry L. Byers, Wayne A. Michaelson 1991-10-22
4996688 Fault capture/fault injection system Larry L. Byers, Kay Tsang, Penny L. Svenkeson 1991-02-26
4989210 Pipelined address check bit stack controller Paul L. Peirson, Michael E. Mayer 1991-01-29
4962501 Bus data transmission verification system Larry L. Byers, Joseba M. Desubijana 1990-10-09
4953131 Unconditional clock and automatic refresh logic David M. Purdham, Larry L. Byers, Terence Sych, Kwisook Tsang 1990-08-28
4926426 Error correction check during write cycles Michael E. Mayer, David M. Purdham 1990-05-15
4918696 Bank initiate error detection David M. Purdham 1990-04-17
4918695 Failure detection for partial write operations for memories Michael E. Mayer, Paul L. Peirson 1990-04-17
4757440 Pipelined data stack with access through-checking — 1988-07-12
4727510 System for addressing a multibank memory system John R. Trost 1988-02-23
4722052 Multiple unit adapter — 1988-01-26
4697233 Partial duplication of pipelined stack with data integrity checking Joseph Meyer, Donald W. Mackenthun 1987-09-29
4652993 Multiple output port memory storage module Gary D. Burns 1987-03-24
4649475 Multiple port memory with port decode error detector — 1987-03-10
4633434 High performance storage unit — 1986-12-30
4600986 Pipelined split stack with high performance interleaved decode Wayne A. Michaelson 1986-07-15
4531213 Memory through checking system with comparison of data word parity before and after ECC processing — 1985-07-23
4357686 Hidden memory refresh — 1982-11-02
4292674 One word buffer memory system — 1981-09-29