Issued Patents All Time
Showing 351–375 of 391 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4959812 | Electrically erasable programmable read-only memory with NAND cell structure | Masaki Momodomi, Riichiro Shirota, Yasuo Itoh, Kazunori Ohuchi, Ryouhei Kirisawa | 1990-09-25 |
| 4943944 | Semiconductor memory using dynamic ram cells | Koji Sakui, Tsuneaki Fuse | 1990-07-24 |
| 4939690 | Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation | Masaki Momodomi, Riichiro Shirota, Yasuo Itoh, Satoshi Inoue, Ryozo Nakayama +1 more | 1990-07-03 |
| 4926382 | Divided bit line type dynamic random access memory with charging/discharging current suppressor | Koji Sakui, Kazunori Ohuchi | 1990-05-15 |
| 4910565 | Electrically erasable and electrically programmable read-only memory | — | 1990-03-20 |
| 4903096 | Semiconductor memory device with barrier layer | Kiyofumi Ochii | 1990-02-20 |
| 4892841 | Method of manufacturing a read only semiconductor memory device | Taira Iwase, Shoji Ariizumi | 1990-01-09 |
| 4893159 | Protected MOS transistor circuit | Youichi Suzuki, Makoto Segawa, Shoji Ariizumi, Takeo Kondo | 1990-01-09 |
| 4855248 | Method of making a semiconductor ROM device | Shoji Ariizumi, Taira Iwase | 1989-08-08 |
| 4814841 | Semiconductor device | Kiyofumi Ochii | 1989-03-21 |
| 4803529 | Electrically erasable and electrically programmable read only memory | — | 1989-02-07 |
| 4798794 | Method for manufacturing dynamic memory cell | Mitsugi Ogura | 1989-01-17 |
| 4779014 | BiCMOS logic circuit with additional drive to the pull-down bipolar output transistor | Kiyofumi Ochii | 1988-10-18 |
| 4748492 | Read only memory | Taira Iwase, Shoji Ariizumi | 1988-05-31 |
| 4737835 | Read only memory semiconductor device | Shoji Ariizumi, Taira Iwase | 1988-04-12 |
| 4725985 | Circuit for applying a voltage to a memory cell MOS capacitor of a semiconductor memory device | Mitsugi Ogura | 1988-02-16 |
| 4710897 | Semiconductor memory device comprising six-transistor memory cells | Kiyofumi Ochii | 1987-12-01 |
| 4706249 | Semiconductor memory device having error detection/correction function | Kaoru Nakagawa, Mitsugi Ogura, Kenji Natori | 1987-11-10 |
| 4687954 | CMOS hysteresis circuit with enable switch or natural transistor | Hiroshi Yasuda, Kiyofumi Ochii | 1987-08-18 |
| 4688064 | Dynamic memory cell and method for manufacturing the same | Mitsugi Ogura | 1987-08-18 |
| 4649412 | Read only semiconductor memory device with polysilicon drain extensions | Taira Iwase, Shoji Ariizumi | 1987-03-10 |
| 4635232 | Semiconductor memory device | Hiroshi Iwahashi | 1987-01-06 |
| 4627153 | Method of producing a semiconductor memory device | — | 1986-12-09 |
| 4616148 | Sense amplifier | Kiyofumi Ochii, Hiroshi Yasuda | 1986-10-07 |
| 4612212 | Method for manufacturing E.sup.2 PROM | Hisakazu Iizuka | 1986-09-16 |