Issued Patents All Time
Showing 176–200 of 249 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5943258 | Memory with storage cells having SOI drive and access transistors with tied floating body connections | Patrick W. Bosshart | 1999-08-24 |
| 5936278 | Semiconductor on silicon (SOI) transistor with a halo implant | Yin Hu, Jarvis Benjamin Jacobs | 1999-08-10 |
| 5917212 | Memory cell with capacitance for single event upset protection | Terence G. W. Blake | 1999-06-29 |
| 5917365 | Optimizing the operating characteristics of a CMOS integrated circuit | — | 1999-06-29 |
| 5909628 | Reducing non-uniformity in a refill layer thickness for a semiconductor device | Amitava Chatterjee, Ih-Chin Chen, Agerico L. Esquirel, Somnath Nag, Iqbal Ali +4 more | 1999-06-01 |
| 5905290 | Single event upset hardened memory cell | — | 1999-05-18 |
| 5795810 | Deep mesa isolation in SOI | — | 1998-08-18 |
| 5703517 | Power reduction in a temperature compensating transistor circuit | — | 1997-12-30 |
| 5617038 | Method and system for screening reliability of semiconductor circuits | — | 1997-04-01 |
| 5615162 | Selective power to memory | — | 1997-03-25 |
| 5600274 | Circuit and method for compensating variations in delay | — | 1997-02-04 |
| 5596286 | Current limiting devices to reduce leakage, photo, or stand-by current in an integrated circuit | — | 1997-01-21 |
| 5565799 | On chip error detection circuit | — | 1996-10-15 |
| 5544101 | Memory device having a latching multiplexer and a multiplexer block therefor | — | 1996-08-06 |
| 5541882 | Method of performing a column decode in a memory device and apparatus thereof | — | 1996-07-30 |
| 5521524 | Method and system for screening reliability of semiconductor circuits | — | 1996-05-28 |
| 5498882 | Efficient control of the body voltage of a field effect transistor | — | 1996-03-12 |
| 5477151 | Capacitor and diode circuitry for on chip power spike detection | — | 1995-12-19 |
| 5469065 | On chip capacitor based power spike detection | — | 1995-11-21 |
| 5461577 | Comprehensive logic circuit layout system | Ching-Hao Shaw, Patrick W. Bosshart, Douglas Matzke, Vibhu Kalyan | 1995-10-24 |
| 5457695 | Method and system for screening logic circuits | — | 1995-10-10 |
| 5438548 | Synchronous memory with reduced power access mode | — | 1995-08-01 |
| 5436173 | Method for forming a semiconductor on insulator device | — | 1995-07-25 |
| 5422852 | Method and system for screening logic circuits | Larry R. Hite, Robert BELL | 1995-06-06 |
| 5406144 | Power reduction in a temperature compensating transistor circuit | — | 1995-04-11 |