Issued Patents All Time
Showing 151–175 of 249 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6424016 | SOI DRAM having P-doped polysilicon gate for a memory pass transistor | — | 2002-07-23 |
| 6376344 | Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device | — | 2002-04-23 |
| 6362058 | Method for controlling an implant profile in the channel of a transistor | — | 2002-03-26 |
| 6362117 | Method of making integrated circuit with closely spaced components | — | 2002-03-26 |
| 6351176 | Pulsing of body voltage for improved MOS integrated circuit performance | — | 2002-02-26 |
| 6308312 | System and method for controlling leakage current in an integrated circuit using current limiting devices | — | 2001-10-23 |
| 6307281 | System and method for reducing power dissipation in a circuit | — | 2001-10-23 |
| 6261886 | Increased gate to body coupling and application to DRAM and dynamic circuits | — | 2001-07-17 |
| 6261879 | Differential SOI amplifiers having tied floating body connections | Patrick W. Bosshart | 2001-07-17 |
| 6255853 | Integrated circuit having dynamic logic with reduced standby leakage current | — | 2001-07-03 |
| 6255854 | Feedback stage for protecting a dynamic node in an integrated circuit having dynamic logic | — | 2001-07-03 |
| 6225175 | Process for defining ultra-thin geometries | — | 2001-05-01 |
| 6207511 | Self-aligned trenched-channel lateral-current-flow transistor | Richard A. Chapman, Keith A. Joyner | 2001-03-27 |
| 6177300 | Memory with storage cells having SOI drive and access transistors with tied floating body connections | Patrick W. Bosshart | 2001-01-23 |
| 6121658 | Deep mesa isolation | — | 2000-09-19 |
| 6118161 | Self-aligned trenched-channel lateral-current-flow transistor | Richard A. Chapman, Keith A. Joyner | 2000-09-12 |
| 6114945 | Apparatus and method for programmable fast comparison of a result of a logic operation with an selected result | — | 2000-09-05 |
| 6096612 | Increased effective transistor width using double sidewall spacers | — | 2000-08-01 |
| 6074920 | Self-aligned implant under transistor gate | — | 2000-06-13 |
| 6069814 | Multiple input buffers for address bits | James H. Liou | 2000-05-30 |
| 6061267 | Memory circuits, systems, and methods with cells using back bias to control the threshold voltage of one or more corresponding cell transistors | — | 2000-05-09 |
| 6045625 | Buried oxide with a thermal expansion matching layer for SOI | — | 2000-04-04 |
| 6043535 | Self-aligned implant under transistor gate | — | 2000-03-28 |
| 6037808 | Differential SOI amplifiers having tied floating body connections | Patrick W. Bosshart | 2000-03-14 |
| 5942781 | Tunable threshold SOI device using back gate well | James B. Burr | 1999-08-24 |